Hi All,I am trying to bring up 10 GBASER PHY in Stratix V FPGA. After setting up the Design based on the reference design provided I am still having trouble with my hi_ber signal. It still remains high while the block lock signal remains high. Kindly give more insights as to the best debug steps for this problem.
Hello Sir,do you set good assigment to?: XCVR_TX_SLEW_RATE_CTRL XCVR_TX_PRE_EMP_1ST_POST_TAP XCVR_TX_VOD OUTPUT_TERMINATION INPUT_TERMINATION XCVR_RX_LINEAR_EQUALIZER_CONTROL INPUT_TERMINATION ?