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Novice
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A10 PCIe-SRIOV IP is not updating the shadow bus interface with MSI-X capability updated

Hi,

We are simulating PCIe SRIOV for A10 with MSI-X. Updates to MSI-X capability register from root port are expected to be updated on shdw interface of the IP as per user-guide. We can see the config transactions going to the SRIOV bridge, but the same updates are not sent on the shdw interface of SRIOV bridge. Though we see the data bus has change of the written values the shdw bus qualifier "ctl_shdw_update" is not asserted by the bridge.

Please find the attached snapshot of the waveform that captures this issue.

 

Thanks,

RamaMohan

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​Hi,

 

Could you please share with us what data that you actually update from the MSI-X Capability register, and how can you confirm it from the HIP interface?

 

Regards -SK

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Novice
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Hi SK, The update is to the MSI-X enable field of message control Register of the MSI-X capability, written from the host (root port). When MSI-X enable/function mask fields of Message control register are updated, the PCIe-SRIOV HIP is expected to send these updates on the control shadow Interface of the IP, which is not happening. I have taken the snapshot of PCIe HIP signals from the simulation waveform dump, which I have shared already in the previous message. The snapshot indicates that the bit[2] of the ctl_shdw_cfg is changing (ctl_shdw_cfg[6:0] changes from 6’h1 -> 6’h5) with the write to MSI-X capability, which set the MSI-X enable field of MSI-C Message Control Register, but ctl_shdw_update is not asserted for this change. Thanks, RamaMohan
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​Hi RomaMohan,

 

Are you using third party BFM to run the simulation? If not, could you please share with us the simulation project, including testbench to run the simulation and further understand the problem?

 

Regards -SK

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Novice
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Hi SK,

Yes, we are using third party BFM for simulations.

 

Thanks,

RamaMohan

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​Hi RamaMohan,

 

Understand you are using third party BFM for simulation and which is unable to share.  I will try to look for if there is any simulation example available from Intel PSG can observe the similar problem here.

 

Regards -SK

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