We are simulating PCIe SRIOV for A10 with MSI-X. Updates to MSI-X capability register from root port are expected to be updated on shdw interface of the IP as per user-guide. We can see the config transactions going to the SRIOV bridge, but the same updates are not sent on the shdw interface of SRIOV bridge. Though we see the data bus has change of the written values the shdw bus qualifier "ctl_shdw_update" is not asserted by the bridge.
Please find the attached snapshot of the waveform that captures this issue.
Could you please share with us what data that you actually update from the MSI-X Capability register, and how can you confirm it from the HIP interface?
Are you using third party BFM to run the simulation? If not, could you please share with us the simulation project, including testbench to run the simulation and further understand the problem?
Understand you are using third party BFM for simulation and which is unable to share. I will try to look for if there is any simulation example available from Intel PSG can observe the similar problem here.