ALTASMI_PARALLEL in full synchro design. Can I use the same clock and edge (rising edge ) for clkin and the rest of the design?

[NJOUB1]

I use a ALTASMI_PARALLEL and a ALTEREMOTE_UPDATE megafunctions in a cyclone III. All the design is full synchro and use a rising edge of a 12MHz clock. I want to know if it's possible to use the same clock (also on rising edge) for clkin of ALTASMI_PARALLEL and clock for ALTREMOTE_UPDATE?

The documentation is not clear!

Thank you for your help.

[Nooraini_Y_Intel]

​​Hi,

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Please do expect some delay in response as most of our agents are out of office due to the year-end holidays. Thank you.

Regards,

Nooraini

[Nooraini_Y_Intel]

Hi NJOUB1,

The answer can be found from the other thread that you have posted:

https://forums.intel.com/s/question/0D50P000049h6wjSAA/altasmiparallel-in-full-synchro-design-can-i-use-the-same-clock-and-edge-rising-edge-for-clkin-and-the-rest-of-the-design

You can use the same clock source as the clock input for both ALTASMI_PARALLEL and ALTEREMOTE_UPDATE megafunction. There is no restriction that you need to use different clock source to each IP/megafunction.

Regards,

Nooraini

[NJOUB1]

Thank you for your answer. When you said same clock source, that imply the same front edge, that right? It's not clear for me when I check the Active Serial Memory Interface (ALTASMI_PARALLEL) Megafunction User Guide (UG-ALT1005-4.2) . For example for a Write : [cid:image001.jpg@01D4A8D6.E2E938F0] [cid:image002.jpg@01D4A8D6.E2E938F0] What is the best solution to manage inputs signals (write , wren, shift_bytes, data_in.....) and to respect the propose timing? 1/ using clk positive edge for signals generation and clk negative edge for ALTASMI_PARALLEL clkin with constraints on Clk Frequency. Or 2/ using same clock positive edge for both with appropriate timing constraints on ALTASMI_PARALLEL. In this case, can-you help me to define the appropriate constraints for the IP? Same question for the ALTEREMOTE_UPDATE IP. Thank you for your help. Regards, Nathalie Schlumberger-Private

[Nooraini_Y_Intel]

Hi Nathalie,

I'm sure what is the difference between 1 and 2. ALTASMI IP sample the signals(write , wren, shift_bytes, data_in.....) on the rising edge of the clkin signal. You can just use the generate the singals base on the rising edge of the clkin signal. As far I checked internally, there are no timing constraint requirement for both ALTASMI_PARALLEL and ALTEREMOTE_UPDATE IP since these are hard block inside the device. There should not be any timing path for hard block inside the device. 

Regards,

Nooraini