ATX PLL profile reconfiguration

[iiwan]

I need in my design for Arria 10 to reconfigure ATX PLL with 3 profiles, 1250,2500,5000 MHz output clock. Configured profiles, enabled embedded streamer and everything other needed as in xcvr user guide.
Also I added jtag_to_avalon_master_bridge. Connected with reconfiguration pins of ATX PLL. And reconfiguration via system console does work. Profiles does not change.
But if I remove jtagtoavalonMB and add internal jtag debug master in ATX PLL reconfiguration with profiles works good. At the end of test I will use my own logic with reconfiguration, not with system console.And my own logic does not work too.
I could not find problem and need help. May be after reconfiguration I have to send mgmt_reset of reconfiguration? Or something not mentioned in documentation?

[iiwan]

P.S. Quartus Prime Standard 18.1 update OS Linux

[Deshi_Intel]

Hi,

From your issue description, could the issue be related to multiple JTAG source design is trying to access ATX PLL reconfig bus causing bus congestion and hence reconfig failure ?

You may want to review your reconfig bus connection again and make sure you are accessing the correct reconfig address space.

I would recommend you to start with sim verification for your actual design that doesn't use system console.

You can also refer to below example link to cross check with your own design

• https://community.intel.com/t5/FPGA-Wiki/Arria10-Transceiver-PHY-Basic-Design-Examples/ta-p/735196

Thanks.

Regards,

dlim

[Deshi_Intel]

HI ,

Are you making any good progress in your debug so far ?

Regards,

dlim

[Deshi_Intel]

HI,

I am setting this case to closure since I never hear back from you after I provided some debug suggestion.

Hopefully you are making progress in your debug effort.

Feel free to file new forum post if you still have further enquiry in future.

Thanks.

Regards,

dlim

[Rk_Athram]

Hi,

did you find solution ?

if yes please share how it solved, as i am also facing same issue 

3 different configuration but atx pll is giving single freq in output!

Please share the solution .

Regards,

Rajesh

[iiwan]

I tested my user logic with reconfiguration, and it works well. So I disabled ADME in ATX PLL and it works well.
If you have questions, my try to help.