Currently I would like to put 16GB DDR4 into operation on an Arria 10. To use the full memory area I have integrated an Address Span Extender (ASE) into the system. Via a clock crossing bridge the Nios can access the windowed slave of the Address Span Extender (32 bit wide) and thus the DDR memory. Due to address space restrictions a single window of 8MB is available, but this is enough for a first start up. The CNTL port of ASE is also connected to the Nios via the CC bridge to move the window in the address space of the DDR. Besides the Nios a SMGDMA can access the windowed slave via the CC Bridge to exchange data from the SDRAM to the DDR4.
Additionally I connected a second MSGDMA over another ASE (512 bit wide, 4GB slave address span) to move data within the DDR memory with higher throughput.
I wrote a short memtest application based on the memtest example to write test data to the whole DDR memory area via the SMGDMA and then read it back to compare it with the original data. Basically the application works as long as I write the same data in every ASE window. If I write individual data for each window this leads to data mismatch. In fact I can only read the last written data.
It seems that I cannot move the AES window correctly over the extended address register/mapping table on the CNTL port. I am aware of the fact that the offsets always have to match the size of the ASE window. But no matter what I write to the registers, only a 0 is read back. So it seems, that I can only work on the first 8MB of the DDR.
The extended address registers of ASE are 64 bit wide to access memory areas >4GB. I set the register with two IOWR_32DIRECT write commands. Is there a corresponding sequence to be followed?
Could the problems be caused by several ASE with different bit widths being connected to the same memory?
Where else could the error be?