Arria V Transceiver Reconfiguration Registers

[Altera_Forum]

Hi, 

 I am new to Altera but have been using Xilinx and to a lesser extent Lattice devices for years, so please forgive me it this is some well known issue I am not privy to yet...  I have a design in a Xilinx device I am attempting to port to an Arria V GX using SerDes. I need o be able to switch speeds dynamically e.g. 1.25Gbp to 2.5Gbps. I am not using the Quartus IDE to do any of this - I prefer to keep things driven by scripts and makefiles to ensure transparency and repeatability. I am currently simulating in Aldec also.  The problem I have is how to actually do this - There seem to be two documented methods: Direct register access using Avalon MM interface and MIF ROM's via streaming. MIF streaming is not an option for me, and the direct register access method is poorly documented ( at least what I have read so far ). I understand how to read and write via the Avalon interface, and there are a few registers documented for direct access, but not all of them. The dynamic reconfiguration guide for example states the local clock dividers can be reconfigured ( /2 /4 /8 etc. ) but I can't find out where these register addresses are in the xcvr_user_gude?  Is here a complete mapping of these registers and the functionality associated with them, something like the DRP mapping in Xilinx SerDes?  Cheers, Gray

[Altera_Forum]

Hey Gray, 

 Did you figure this out yet?  I didn't respond earlier as I was working on an Arria V GZ testbench to see if I could get the Transceiver Toolkit components working in Modelsim;  http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html  There wasn't a GZ example in there, but I've got something working now (Quartus 14.0 + Modelsim-SE 10.3b).  Here's the testbench output, which has messages that cross-reference to the documentation for the registers;  # ===============================================================# Arria V GZ Custom PHY Qsys System Testbench# ===============================================================# # 0: verbosity_pkg.set_verbosity: Setting Verbosity level=4 (VERBOSITY_INFO)# * Deassert reset# gx_link_test_system_tb.dut.avalon_st_adapter_001.timing_adapter_0: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.# gx_link_test_system_tb.dut.avalon_st_adapter.timing_adapter_0: The downstream component expects valid data, but the upstream component cannot provide it.# # -----------------------------------------------# 1: Wait for the transceivers to initialize.# -----------------------------------------------# # Wait for reconfig busy to deassert# # Wait for 1 us# # -----------------------------------------------# 2: Read the Custom PHY registers.# -----------------------------------------------# # Registers per Ch. 9 Custom PHY IP Core (xcvr_user_guide.pdf)# # Table 9-21: PMA Common Control and Status Registers# (00000088h, 00000001h)# # Table 9-22: Reset Control Registers - Automatic Reset Controller# (00000104h, 00000001h)# (00000108h, 00000003h)# # Reset status:# -> TX is ready.# -> RX is ready.# # Table 9-23: Reset Controls - Manual Mode# (00000110h, 00000000h)# # Table 9-24: PMA Control and Status Registers# (00000184h, 00000000h)# (0000018ch, 00000001h)# (00000190h, 00000000h)# (00000194h, 00000000h)# (00000198h, 00000001h)# (0000019ch, 00000001h)# # Table 9-25: Custom PCS# (00000200h, 00000000h)# (00000204h, 0000003eh)# (00000208h, 00000000h)# (0000020ch, 00000000h)# (00000210h, 00000000h)# (00000214h, 00000000h)# # -----------------------------------------------# 3: Read the reconfiguration controller registers.# -----------------------------------------------# # Registers per Ch. 16 Transceiver Reconfiguration Controller IP Core (xcvr_user_guide.pdf)# # Table 16-9: PMA Analog Registers# (00000820h, 00000000h)# (00000828h, 00000000h)# (0000082ch, 00000000h)# (00000830h, 00000000h)# # Table 16-11: EyeQ Monitor Registers# (00000840h, 00000000h)# (00000848h, 00000000h)# (0000084ch, 00000000h)# (00000850h, xxxxxxxxh)# # Table 16-13: DFE Registers# (00000860h, 00000000h)# (00000868h, 00000000h)# (0000086ch, 00000000h)# (00000870h, 0000xxxxh)# # Table 16-15: AEQ Registers# (000008a0h, 00000000h)# (000008a8h, 00000000h)# (000008ach, 00000000h)# (000008b0h, 00000000h)# # Table 16-17: ATX Tuning Registers# (000008c0h, deadbeefh)# (000008c8h, deadbeefh)# (000008cch, deadbeefh)# (000008d0h, deadbeefh)# # Table 16-24: MIF Streamer Module Registers# (000008e0h, 00000000h)# (000008e8h, 00000000h)# (000008ech, 00000000h)# (000008f0h, 00000000h)# # Table 16-19:PLL Reconfiguration Registers# (00000900h, 00000000h)# (00000908h, 00000000h)# (0000090ch, 00000000h)# (00000910h, 00000000h)# # Table 16-21: DCD Calibration Registers# (00000920h, 00000000h)# (0000092ch, 00000000h)# (00000930h, 00000000h)# # -----------------------------------------------# 4: Read the pattern generator registers.# -----------------------------------------------# # Registers per Ch. 36 Avalon Streaming Data Pattern Generator and Checker Cores (ug_embedded_ip.pdf)# # Table 36-3: Data Pattern Generator Core Register Map# (00000a20h, 000000Xch)# (00000a24h, 00000001h)# (00000a28h, 00000000h)# (00000a2ch, 00000000h)# (00000a30h, 00000000h)# (00000a34h, 00000000h)# (00000a38h, 00000000h)# (00000a3ch, 00000000h)# # -----------------------------------------------# 5: Read the pattern checker registers.# -----------------------------------------------# # Registers per Ch. 36 Avalon Streaming Data Pattern Generator and Checker Cores (ug_embedded_ip.pdf)# # Table 36-10: Data Pattern Checker Core Register Map# (00000a00h, 000000X8h)# (00000a04h, 00000001h)# (00000a08h, 00000100h)# (00000a0ch, 00000000h)# (00000a10h, 00000000h)# (00000a14h, 00000000h)# (00000a18h, 00000000h)# (00000a1ch, 00000002h)# # -----------------------------------------------# 6: Transceiver test.# -----------------------------------------------# # Enable the pattern generator (PRBS7)# Write (00000a20h, 000000Xdh)# Read (00000a20h, 000000Xdh)# # Enable the pattern checker (PRBS7)# Write (00000a00h, 000000X9h)# Read (00000a00h, 000000X9h)# # Wait for 1 us# # -----------------------------------------------# 7: External loopback status.# -----------------------------------------------# # Table 36-10: Data Pattern Checker Core Registers# (00000a00h, 000000Xbh)# (00000a04h, 00000001h)# (00000a08h, 00000100h)# (00000a0ch, 00000000h)# (00000a10h, 00000000h)# (00000a14h, 00000000h)# (00000a18h, 00000000h)# (00000a1ch, 00000002h)# # Reset status:# -> TX is ready.# -> RX is ready.# # Pattern checker lock# -> The pattern checker is locked.# # -----------------------------------------------# 8: Internal loopback test.# -----------------------------------------------# # Enable internal loopback by setting phy_serial_loopback = 1 (Table 9-24: PMA Control and Status registers, xcvr_user_guide.pdf)# Write (00000184h, 00000001h)# Read (00000184h, 00000001h)# # Wait for 1 us# # Reset status:# -> TX is ready.# -> RX is ready.# # Pattern checker lock# -> The pattern checker is locked.# # -----------------------------------------------# 9: PRBS15 test.# -----------------------------------------------# # Disable the pattern generator# Write (00000a20h, 000000Xch)# gx_link_test_system_tb.dut.avalon_st_adapter.timing_adapter_0: The downstream component expects valid data, but the upstream component cannot provide it.# Read (00000a20h, 000000Xch)# Enable the pattern generator for PRBS15# Write (00000a24h, 00000002h)# Write (00000a20h, 000000Xdh)# Read (00000a20h, 000000Xdh)# # Wait for 1 us# # Reset status:# -> TX is ready.# -> RX is ready.# # Pattern checker lock# -> The pattern checker is *NOT* locked.# # Disable the pattern checker# Write (00000a00h, 000000X8h)# gx_link_test_system_tb.dut.avalon_st_adapter_001.timing_adapter_0: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.# Read (00000a00h, 000000X8h)# # Enable the pattern checker for PRBS15# Write (00000a04h, 00000002h)# Write (00000a00h, 000000X9h)# Read (00000a00h, 000000X9h)# # Wait for 1 us# # Reset status:# -> TX is ready.# -> RX is ready.# # Pattern checker lock# -> The pattern checker is locked.# # ===============================================# Simulation complete.# ===============================================# # ** Note: $stop : gx_link_test_system_tb.sv(744)# Time: 39845 ns Iteration: 0 Instance: /gx_link_test_system_tb# Break in Module gx_link_test_system_tb at gx_link_test_system_tb.sv line 744   I have not looked at changing the lane rate, but from what I've read it should be possible.   I plan on documenting what it takes to get the transceiver simulated, so if you want, I can post an initial version of the simulation code. You can then modify it to test the lane rate changes.  Regarding MIF files; I have not used them yet, but I saw documentation in AN676 and Ch 16 of the Transceiver Users Guide.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Apologies for not replying sooner, I was ill three days last week...  This is brilliant - I don't know if these registers map the same for the GX but I shall check the documents referenced again and see what I can find, thanks! I have the simulation running already at a given speed, communicating with a Xilinx SerDes that I modelled some time ago. It is just the rate change I'm not clear on how to initiate.  Cheers, Gray

[Altera_Forum]

So these are the registers that I had found before, but surely there must be more? 

 For example the PLL reconfiguration registers don't reconfigure the PLL at all, they merely switch the reference clock or the PLL used to a different PLL. In my case of 4 SerDes links, each supporting 5 line rates ( all the same rates, but can't be bonded if the PLL is to be reconfigured ) that would mean using 20 PLL's or more reference clocks or a combination to keep count down... not really practical. There is also mention in the dynamic reconfiguration guide that the local clock dividers can be reconfigured ( /2 /4 /8 etc. ) but I don't see this listed either. This is really what I need I guess, the registers needed that will reconfigure the PLL or possibly the PMA, I have a hard time believing that the PLL's are simply switched to achieve a line rate change! :-)  Cheers, Gray

[Altera_Forum]

Hi Gray, 

  --- Quote Start ---  So these are the registers that I had found before, but surely there must be more?  For example the PLL reconfiguration registers don't reconfigure the PLL at all, they merely switch the reference clock or the PLL used to a different PLL. In my case of 4 SerDes links, each supporting 5 line rates ( all the same rates, but can't be bonded if the PLL is to be reconfigured ) that would mean using 20 PLL's or more reference clocks or a combination to keep count down... not really practical. There is also mention in the dynamic reconfiguration guide that the local clock dividers can be reconfigured ( /2 /4 /8 etc. ) but I don't see this listed either. This is really what I need I guess, the registers needed that will reconfigure the PLL or possibly the PMA, I have a hard time believing that the PLL's are simply switched to achieve a line rate change! :-)   --- Quote End ---   I have not tried to implement lane rate changes yet. I was focused on getting a design to work with the "Transceiver Toolkit", and it turns out the GUI is broken in Quartus II 14.0 (but it works correctly in 13.1).  I have an example design document for the TI TSW14J56 development board (which contains an Arria V GZ), and that example can implement lane rate changes. In that design they discuss the fact that the CMU PLL is used by the transceivers, and an fPLL is used by the FPGA fabric. The CMU PLL settings are modified by streaming a MIF file, and the TI document references AN676 for details.  So it sounds like there are no registers for CMU PLL programming, and that you have to stream MIF files. I don't think this is actually that hard. The Custom PHY Qsys component has an Avalon-MM master for reading MIF files, so you just need to connect a RAM to that interface and to another master (eg., JTAG-to-Avalon-MM) and then use that second master to write the MIF contents, and then trigger a MIF read by the reconfiguration controller.  Cheers, Dave

[Altera_Forum]

Hi all 

 Did you manage to control the clock dividers? I'm trying to reconfigure just one channel switching between two CMU PLL's and every time I switch my transmitter PLL(I'm testing in loopback mode) my CDR stops working. I suspect it could be that the CDR must be set up with the new data rate, but I don't know how. I'm switching PLL's with the register based method. Controlling the clock dividers would be an easy way to do it, as the new data rates are related to the first one.  I tried also the streamer based method, but it just didn't work. And I would have another question. Does the MIF streaming configures both TX PLL and CDR blocks or only the transmitter PLL?  Cheers Edu