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Altera_Forum
Honored Contributor I
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Arria ii Gx Remote Update Giving Pof Error once it get error

Hi, 

I using arria ii gx fpga with epcs128 flash attached. I Using altera remote update and parallel mega functions for upgrade epcs over processor. i have divided flash into 3 pages. page0 has factory .pof which will only to check pof of pag2 and page1 and switch respectively on error status. and pag1 and page2 has application image. my job is to upgrade the page2 from page1. 

 

Well, Consider the scenario i have programmed the ecps with the two page, page0 and page1 and i boot then FPGA get successfully got the pof error and gone to page1, since i have diverted page1 if there is no data at page2 in epcs. if i try to update epcs page2 via processor through, it got written all the .rbf data. if i give power cycle then the fpga page0 update function giving a pof error and going to page1. if i do this scenario it not at all loading the upgrade image. 

 

Ok, Next scenario i have created epcs .pof with the 3 pages. and programmed. following boot fpga get loaded with the page2. so it means it not getting .pof error and going to page2. fine, now i started to upgrade the page2 via processor over fpga. then the fpga can successfully updated the epcs page2, on the next boot fpga got loaded the page2, which i have updated last from processor.  

 

Followed i started to updated again the pages2 and booted, then the fpga got loaded page1 image.... pof error.  

 

Then i have examine the epcs data and checked in the hex editor there is data got updated on the location i specified at page2. 

 

As Arria ii gx errata say it will update circuitry will give error when there is no pof on the jumping location, half image written or crc error... 

 

Now my questions are: 

1. Why fpga is giving the pof error once it gets the pof error ? if it will give continuous error how i can stop it ? i checked in signal tap the nstatus and pof error continuous toggling and jumping to page1 once it gets an error. 

 

2. Is it possible to update the image at page2, at the time, fpga has page1 image ?  

 

3. Why it only updating page2, when i load the image from papge2. and following updates falling ? 

 

I using .rbf file to update the epcs via fpga from processor. Page0:Addr:0x000000, Page1:Adr:0x240000 and Page2:Adr:0x800000; All .sof are compressed while creating consolidated .pof 

 

suggestions and approach are highly appreciated. 

 

Sorry for my poor English  

 

Thanks, 

Shivaji M
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Altera_Forum
Honored Contributor I
42 Views

Hi All, 

After many trial we found the solution. it just maters what frequency you running parallel function. we observed there is signal integrity issue on the board. which causing the crc to fail at the boot up and showing the pof error. so we have reduce the frequency in khz and sorted out the issue. Now its working with the two pages+ 3 pages even smoothly with all the test cases we planned. 

 

Thanks, 

Shivaji M
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