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Avalon MM Slave - What's the simple way to extract the above lines from QSYS to HDL?

Amir3
New Contributor I
492 Views

Hi,

What's the simple way to extract Avalon MM lines from QSYS to HDL?

The goal is to connect the component I am preparing as another Slave on the Bus while the Master remains the NIOS. I will implement the side of the Avalon MM Slave communication in the component.

In addition, I would love to hear more ideas on how to properly / efficiently connect NIOS to non-QSYS components.

Thanks and good day

 

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MathiasB
New Contributor I
480 Views

Hi,

 

The proper way in my opinion would be to instantiate a "Avalon-MM Pipeline Bridge" IP in your Qsys.

You connect its slave interface to the Nios master and export IP's master side.

When you instantiate the qsys in your hdl, the Avalon signals will be there for you to connect to your component.

 

As for your other question, what are you trying to do? I would say you can simply export anything from your Qsys to wherever it is instantiated.

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MathiasB
New Contributor I
481 Views

Hi,

 

The proper way in my opinion would be to instantiate a "Avalon-MM Pipeline Bridge" IP in your Qsys.

You connect its slave interface to the Nios master and export IP's master side.

When you instantiate the qsys in your hdl, the Avalon signals will be there for you to connect to your component.

 

As for your other question, what are you trying to do? I would say you can simply export anything from your Qsys to wherever it is instantiated.

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Amir3
New Contributor I
475 Views

I'm just trying to properly connect the Avalon MM BUS to the comp I make in VHDL code.

Following the solution you proposed with the "Avalon-MM Pipeline Bridge", I read on the Internet that it is possible to produce a component in QSYS that simply connects the BUS to HDL directly. On the one side it connects to the BUS as a Slave and on the other side it connects the same signals of the Avalon MM Slave and allows the above signals to be output to HDL. Do you recommend this implementation?

Amir3_0-1639065144350.png

 

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sstrell
Honored Contributor III
466 Views

I think you are referring to simply exporting an interface.  Any interface in Platform Designer can be exported so it can be connected to the rest of your Quartus project (when instantiating the Platform Designer system elsewhere in your project hierarchy) or directly to I/O pins (if your system is to be the top level of your Quartus project).  You can see from the instantiation template, available in the Generate menu in Platform Designer, what signals would be in your port mapping when you export an interface and then instantiate the system.

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MathiasB
New Contributor I
471 Views

I am not sure I understand what you mean. Do you have a link to where you read about this component?

 

Otherwise, what I suggested applies if you want to connect your slave component outside of Qsys (eg: the qsys and the component are both instantiated in a top module).

But if you want to, you can directly put your VHDL component inside the Nios' Qsys and connect the Avalon interfaces like any other IP. To do this, you have to generate a _hw.tcl file for your module. Then it appears in Qsys' IP catalog.

 

I would say it is easier to connect everything inside Qsys, because it can automatically add protocol converters if needed.

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Amir3
New Contributor I
439 Views

Thank you, you helped me a lot!

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