Avalon Streaming Interface with FIR

[Altera_Forum]

I have the following outputs from an FIR 

 I’ve got a question relating to the FIR compiler 9.1. The picture shows Source_Valid Source_SOP Source_EOP Source_Channel  Source_Ready is pulled high  Sweep This is a 2 channel parallel implementation  Sweep2 This is a 2 channel serial implementation  The problem is that EOP should only be 1 clock cycle.

[Altera_Forum]

It is only one clock cycle. Both SOP and EOP must be qualified with VALID. so real_eop = eop & valid. 

 Jake

[Altera_Forum]

Ok, thanks, 

 I was just a little concerned that the output signals I was getting didn't look like examples in the FIR compiler manual.

[Altera_Forum]

do u know where can i get sources which help me in understand the avalon streaming source for design digital filter to implement into FPGA cyclone2? 

 tq ya