BIOS does not detect our PCIe card

[Altera_Forum]

Hi there, 

 We have a PCIe design on Stratix IV working well when compiled on QII 11.0, but stopped working when compiled from QII 12.1 SP1. Both compile successfully, only that the image generated from 12.1 seems to be undetectable by BIOS.  The IP has been regenerated in MegaWizard before compiling in 12.1.  Couldn't figure out what we did wrong in the compilation process of 12.1, may have to debug the behavior of the card directly. Any suggestions?  Thanks, Hua

[Altera_Forum]

I had an issue with the ALTGX_RECONFIG component created in the 11.1sp1 tools. It was necessary to regenerate the component in 12.1sp1 to resolve the issue. According to my Altera Service Request "This issue had been fixed in Quartus versuib 12.0 B78 onward." You comment that you are using 12.1 - so this issue should have been resolved in your tools - but to be sure, could you install 12.1sp1? 

   --- Quote Start ---   The IP has been regenerated in MegaWizard before compiling in 12.1.   --- Quote End ---   Can you confirm this by looking at the header information in the generated files.   There is a command-line tool that you can run to refresh/regenerate MegaWizard IP. I forget what its called - look in the Quartus handbook, its in there somewhere.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Thank you for your quick response!  We are indeed using QII 12.1sp1, and the first line of the generated vhd file also indicates it was generated from 12.1:  -- megafunction wizard: %IP Compiler for PCI Express v12.1%  I also double checked the MegaWizard configurations page by page against the copy that worked (and compiled in 11.0), they are the same.  Basically we supplied the same source files and configuration files as far as I can tell, to two different compilation processes (11.0 vs 12.1sp1), both compiled successfully but one image fails to be detected by BIOS.   Is there anything in the hard core that I can use signaltap to check if the it is in working condition? Like checking the link status or something like that?  Thanks, Hua

[Altera_Forum]

Hi Hua, 

  --- Quote Start ---   We are indeed using QII 12.1sp1, and the first line of the generated vhd file also indicates it was generated from 12.1:  -- megafunction wizard: %IP Compiler for PCI Express v12.1%  I also double checked the MegaWizard configurations page by page against the copy that worked (and compiled in 11.0), they are the same.   --- Quote End ---   Using a file-difference program would be easier :)  Did you check the ALTGX_RECONFIG component?  Have you read through the document I wrote and posted with this thread:  http://www.alteraforum.com/forum/showthread.php?t=35678  I haven't tried these designs with 12.1sp1, but I know they worked with the tools I used when I wrote the document. You could download the code and check it out.    --- Quote Start ---   Basically we supplied the same source files and configuration files as far as I can tell, to two different compilation processes (11.0 vs 12.1sp1), both compiled successfully but one image fails to be detected by BIOS.   Is there anything in the hard core that I can use signaltap to check if the it is in working condition? Like checking the link status or something like that?   --- Quote End ---   Check the configuration controller completes its reset sequence. The PDF in the thread linked to above has some SignalTap II traces you can try to re-produce.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I actually couldn't find ALTGX_RECONFIG being used in the PCIe IP files. We are using PCIe hardcore but it is Mega Wizard based. The reconfiguration support must have been encapsulated in the generated IP. So if we regenerate the IP in 12.1sp1, it "should" fix the problem you mentioned in post# 2.  I am in the process of going through the thread you posted in post# 4 right now.  Thanks again for the help!  Regards, Hua

[Altera_Forum]

--- Quote Start ---   I actually couldn't find ALTGX_RECONFIG being used in the PCIe IP files. We are using PCIe hardcore but it is Mega Wizard based. The reconfiguration support must have been encapsulated in the generated IP.    --- Quote End ---   Then you have *incorrectly* implemented your PCIe design in the Stratix IV device; its the users responsibility to also include the ALTGX_RECONFIG component and connect it to the PCIe core.  Look at the designs in the PDF I linked to, eg., look at Figure 1(b). Those designs were implemented in a Stratix IV.  Cheers, Dave

[Altera_Forum]

I think you may have helped us finding the problem.  

 I went deeper in our code and found the ALTGX_RECONFIG (or a file called altpcie_reconfig_4sgx.v, which was generated automatically by QII 11.0), and it still appears to be generated by 11.0.   Our design was based on the chaining DMA example coming with the IP compiler for PCI Express v11.0. We added our designs into its framework so we had to use a lot of their IPs, altpcie_reconfig_4sgx.v included. It looks like when we regenerate IP Compiler for PCI Express to v12.1, those design examples were not automatically regenerated.  Will follow this lead and see what happens.

[Altera_Forum]

--- Quote Start ---   Will follow this lead and see what happens.  --- Quote End ---    Look at the example in the PDF and its associated code. The code shows how to connect the IP blocks. Pay attention to the reset logic too, you must make sure to synchronize it correctly.  Cheers, Dave