Bonded Mode support for GXT transceivers in L-tile stratix 10 FPGA

[HBhat2]

Hi,

I was referring to AN778 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an778.pdf

I was checking the guidelines regarding bonded mode (x2) using GXT channels. I am using Stratix 10 SX SoC dev kit which has L-tile transceiver. In AN778, there is a chapter "2.1.2.2. Bonded GX Channels ". However, there is no information for Bonding the GXT transceivers.

I am aware of GXT lanes are not continuous (i.e. ch0,1, 3 and 4 can be GXT channels in bank 1 and 3). With this only x2 bonding is possible (considering the channel number continuity). I want to know whether x2 bonding is allowed in GXT transceivers or bonding option is not available for L-tile GXT transceivers.

With Regards,

HPB

[Nathan_R_Intel]

Hi, Bonding is not supported for GXT transceivers for both L-tile and H-tile. This is covered in section 3.3.4 in Stratix 10 Phy USer Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf Regards, Nathan

[HBhat2]

Hi @NathanR_Intel​ ,

Yes, That was my specific question. 3.3.4 of user guide says the ATX PLL can drive the no. of non-bonded channels. But, I did't find any statement in the S-10 XCVR PHY user guide which states that L-tile XCVRs doesn't support bonding mode. If I configure XCVR L-tile native PHY in the platform designer tool with Bonded mode for GXT, I am not seeing any error message (for S-10 SoC dev kit) saying that Bonded mode is not supported for L-tile XCVRs. As I am possessing incomplete information regarding XCVR PHY bonded mode support, I am looking for a document support explicitly describing the Bonded mode is supported or L-Tile native PHY in S-10.

With regards,

HPB

[HBhat2]

Hi @NathanR_Intel​ ,

As I know, Channel Bonding is the feature of PCS. I want to write a custom PCS, then whether I can write a custom logic to take care channel Bonding? What are the dependencies of channel bonding wrt PMA block?

With regards,

HPB

[HBhat2]

Hi @NathanR_Intel​ ,

https://www.youtube.com/watch?v=PxAx_xR_iJA

In this training video "Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer", the material says that Bonding mode can be configured for L tile / H-tile XCVR PHY.

With Regards,

HPB

[Nathan_R_Intel]

Hie Hariprasad, My apologies, my previous answer was not clear enough. Let me answer your questions and provide additional explanation. Question: As I am possessing incomplete information regarding XCVR PHY bonded mode support, I am looking for a document support explicitly describing the Bonded mode is supported or L-Tile native PHY in S-10. Answer: Refer to Section 3.3 (Transmitter Clock Network) in User Guide Also refer to section 3.9 on Channel Bonding for more details. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf The section covers what is bonded vs non-bonded channel configuration. Bonded configuration : Both high speed serial clock and low speed parallel clock from PLL is routed to all transmitter channels. Non-bonded configuration: Only high speed serial clock from PLL routed to all transmitter channel. The low speed parallel clock is generated using local divider in the channel, thus contributing to higher channel to channel skew - x1 and GXT clock line only support non-bonded configuration. -x6 and x24 clock line support bonded configuration and non-bonded configuration. Questions: "But, I did't find any statement in the S-10 XCVR PHY user guide which states that L-tile XCVRs doesn't support bonding mode." Answer: There is none as L-tile XCVR supports both bonding mode and non-bonded mode. When channel used as GX channel, both bonded and non-bonded is supported. This is documented in section 2.1.2 of AN778. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an778.pdf When channel used as GXT channel, it needs to use GXT clock line for high data rates whereby only non-bonded is supported. This is covered in section 3.3.4 of user guide which states that ATX PLL can drive upto 4GXT channels in non-bonded mode for GXT clock network. However if use GXT channels with lower data rates and using bonded mode; Quartus Prime Pro will use the x6 or x24 clock line and allow successfull compilation. Hence, please take note the limitation of allowing bonded vs non-bonded is on the Transmitter Clock Network. I will provide feedback to Intel documentation team to make this message more clear in the user guide. Refer to Table 39 in Stratix 10 datasheet to determine the maximum data rate supported by each clock line. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf Question: If I configure XCVR L-tile native PHY in the platform designer tool with Bonded mode for GXT, I am not seeing any error message (for S-10 SoC dev kit) saying that Bonded mode is not supported for L-tile XCVRs. Answer: This could be because you data rate is lower allowing Quartus Prime Pro to used x6 or x24 clock line. If your data rate is higher than 17.4Gbps, then this is because the Native Phy IP System Messages does not error this out. You will need to perform full compilation to observe error in fitter. Question: As I know, Channel Bonding is the feature of PCS. I want to write a custom PCS, then whether I can write a custom logic to take care channel Bonding? What are the dependencies of channel bonding wrt PMA block? Answer: Refer to Section 3.9 in user guide to understand Channel Bonding. Stratix 10 supports both: - PMA bonding and - PMA and PCS bonding. Hence, channel bonding is not a feature of PCS alone. If you are writing a custom PCS, you only can take care of the PCS bonding, not the PMA bonding. You will need to configure the PMA to handle the PMA bonding. Channel bonding on the PMA is dependent mainly on the Transmitter Clock Line user, Transmitter PLL used and whether the master clock divider is used. If master clock divider is not used, then there is no PMA bonding. Regards, Nathan

[HBhat2]

Hi Nathan,

"This could be because you data rate is lower allowing Quartus Prime Pro to used x6 or x24 clock line. If your data rate is higher than 17.4Gbps, then this is because the Native Phy IP System Messages does not error this out. You will need to perform full compilation to observe error in fitter."

You are right. I get the error while configuring the ATX PLL with master CGB

Also, I am seeing same behaviour for an H-tile device also.

I think even H-tile transceiver doesn't support x2 bonded mode for more than 17Gbps.

The reason being, I created the project for H-tile S-10 FPGA (1SX280HUF50E1...) and in the platform designer I am getting the error " Master CGB input clock frequency (9667.96875MHz) is above maximum allowed (8700MHz).

So, my conclusion is either L-tile or H-tile XCVR doesn't support x2 bonded mode for more than 17Gbps link rate.

With Regards,

HPB 

[HBhat2]

Hi,

I have some ~20ns skew tolerance between 2 channels. I want to know what would be the data skew between 2 adjacent TX channels (PMA skew).

With regards,

HPB

[Nathan_R_Intel]

Hie, Your following conclusion is correct: "So, my conclusion is either L-tile or H-tile XCVR doesn't support x2 bonded mode for more than 17Gbps link rate." As for channel skew, it depends on the clocking and device used. Please refer to Stratix 10 datasheet link below https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf Table 43 for L-tile and Table 54 for H-tile. Regards, Nathan