CXL Example Design simulation: Illegal combination of drivers

[Raj_G]

Hi,

Running the simulation of the CXL Example Design, following the CXL_Reference_Designs_User_Guide_v1.5.pdf document, gives the following errors during elaboration:

Error-[ICPD_INIT] Illegal combination of drivers

The same error is caught on the following files:

cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/cxl_memexp_sip_rst_ctrl.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/bbs_wrapper.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/bbs_top.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/cxl_io_top.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_100/sim/soft_wrapper/rnr_cxl_rx_aib_deskew_sm.sv, 24
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_100/sim/soft_wrapper/rnr_cxl_reset_ctrl.sv, 24

All these 6 files are encrypted, so it is not possible to confirm if the violation is real.

The environment uses:

Quartus 2.23 (also tried with 2.24, but got the same result)
Synopsys VCS T-2022.06-SP2-1
Avery BFM v2.5

Has anyone encountered the same situation? Any suggestions on how to debug the issue?

Thank you,

Ricardo.

[JohnT_Intel]

Hi,

The procedure is the same for both VCS and VCSMX. It is more on the environment will be pointing towards VCXMX.

[JohnT_Intel]

Hi,

Attach is the logfile from my side. May I know what is the different environmennt changes you make that change the error message? The initial error message is related to illegal driver issue.

[RicardoC]

Hi John,

Thank you for the log file.

Progress has been made. I found out that some source files of the int_0_ip_filelist.f file list were not being compiled. As you can see in the log files I attached before, no errors were thrown by VCS during compilation, but the not all files are listed as "Parsing". After a lot of experimentation, I figured out that the option "-kdb" was the cause of compilation failure (a google search shows that there are other cases of issues compiling protected files using VCS with the -kdb option (kdb allows the creation of structure information in VCS for Verdi usage)). Once I removed that option, the compilation completes and elaboration advances. The elaboration error then changed to the original issue of this topic - illegal combination of drivers (to answer your question, the original error existed with the removal of support for Verdi, which you later clarified it was not supposed to be done).

I decided to downgrade our version of VCS to the version of VCS that I got from your log file (2019), and that caused the error of "illegal combination of drivers" to disappear. Note that we are using VCS but you are using VCS Mx.

Simulation now runs, but it is exiting prematurely with:

*Verdi* FSDB WARNING: *FATAL ERROR* Rewinding time is prohibited. Time creation should be skipped.

I'm not sure if this is due to the removal of the -kdb option or not. Any suggestions?

Would you be able to rerun your sim without the -kdb to see if it's going to fail the same way? 

I'm attaching the sim.log for your reference.

Thank you,

Ricardo.

[OliverJacob12]

---

@RicardoC wrote:

Hi John,

Thank you for the log file.

Progress has been made. I found out that some source files of the int_0_ip_filelist.f file list were not being compiled. As you can see in the log files I attached before, no errors were thrown by VCS during compilation, but the not all files are listed as "Parsing". After a lot of experimentation, I figured out that the option "-kdb" was the cause of compilation failure (a google search shows that there are other cases of issues compiling protected files using VCS with the -kdb option (kdb allows the creation of structure information in VCS for Verdi usage)). Once I removed that option, the compilation completes and elaboration advances. The elaboration error then changed to the original issue of this topic - illegal combination of drivers (to answer your question, the original error existed with the removal of support for Verdi, which you later clarified it was not supposed to be done).

I decided to downgrade our version of VCS to the version of VCS that I got from your log file (2019), and that caused the error of "illegal combination of drivers" to disappear. Note that we are using VCS but you are using VCS Mx.

Simulation now runs, but it is exiting prematurely with:

*Verdi* FSDB WARNING: *FATAL ERROR* Rewinding time is prohibited. Time creation should be skipped.

I'm not sure if this is due to the removal of the -kdb option or not. Any suggestions?

Would you be able to rerun your sim without the -kdb to see if it's going to fail the same way? 

I'm attaching the sim.log for your reference.

Thank you,

Ricardo.

---

Running the simulation of the CXL Example Design, following the CXL_Reference_Designs_User_Guide_v1.5.pdf document, gives the following errors during elaboration:

Error-[ICPD_INIT] Illegal combination of drivers

[JohnT_Intel]

Attach is the log

[RicardoC]

Hi John,

I downgraded the version of Verdi to 2019, as show in your elaboration log file, and this allowed the code to be compiled with the -kdb option enabled. The simulation runs longer than before, but it fails with:

UVM_ERROR /fpga/P-2019.06-SP2-6/cxltyp3ddr_tb_22p4/tb/tests/cxl_base_test_eot_checks.svhp(43) @ 593702.342ns: uvm_test_top [CXL_REPORT] CFG_CORERRSTS is 0x4001

I've attached the complete simulation log file for your reference.

Any recommendations?

Thank you,

Ricardo.

[JohnT_Intel]

Hi,

Can you check if you have the UVM library opn your VCS simulation tools?

[RicardoC]

Hi John,

The UVM library was compiled with the testbench and a grep "uvm-1.2" in the log file that I sent shows prints from different UVM files, as well as the $finish that was called from one of them:

[run]$ grep uvm-1.2 sim.log
UVM_INFO /shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2/src/base/uvm_root.svh(412) @ 0: reporter [UVM/RELNOTES] 
UVM_INFO /shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2/src/base/uvm_resource.svh(564) @ 0.000000 ns: reporter [UVM/RESOURCE/ACCESSOR] reads: 0 @ 0.000000 ns writes: 1 @ 0.000000 ns
UVM_INFO /shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2/src/base/uvm_report_catcher.svh(705) @ 593702.342ns: reporter [UVM/REPORT/CATCHER] 
UVM_INFO /shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2/src/base/uvm_report_server.svh(894) @ 593702.342ns: reporter [UVM/REPORT/SERVER] 
$finish called from file "/shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2/src/base/uvm_root.svh", line 613.
[run]$ echo $UVM_HOME
/shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2
[run]$ file /shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2/src/base/uvm_root.svh
/shared/opt/synopsys/vcs/P-2019.06-SP2-6/etc/uvm-1.2/src/base/uvm_root.svh: C++ source, ASCII text
[run]$ 

Thank you,

Ricardo.

[JohnT_Intel]

Hi,

So you are seeing the same error even if you are able to echo the UVM environment?

[RicardoC]

Hi,

Yes. I saw the error with the echo of UVM environment. The grep command was run on the log file of the simulation. The path in the log file comes from the environment variable.

Thanks,

Ricardo.

[JohnT_Intel]

Hi,

I have receive update from FAE that you have resolved the issue.

[RicardoC]

Hi,

That's not correct. The simulation runs with errors, as you can see in the log file sent above.

Thanks,

Ricardo.