FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Can the PCI Express Hard IP support, not RP nor EP, but instead "Switch" Mode?


In our DSP board we can run our PCIe enumeration from NIOS2/RTEMS against a Root Port PCIe Hard IP in an upstream port, but would like to use the same hardware build in a downstream port exposing one or two BARs. When we try this the Root Port PCIe Hard IP appears to respond to all configuration requests flagging not-supported.


It would be nice to deploy the identical hardware build so that it can assume the switch upstream root complex role and or a switch down stream 2 BAR type 1 device role that does not perform the bus enumeration. Presumably this is what the CPU board designs do when their board occupies a down-stream port of of a switch?


Is there a, not root port nor end point mode, but instead "switch" mode for the PCIe hard IP, or perhaps can the mode of the hard IP be dynamically reconfigured?



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Hi Jhill1,


All the FPGA device PCIE HIP does not have the capability to be dynamically change between Root Port to End Point role and vice versa. The PCIe HIP must be configured and act as the Root Port (Host) in the system or must be configured and act as the End Point at a time after power up, enumerate and enter link active state. In the PCIe IP, you can only choose the option either Root Port or Native endpoint as the Port type. There is no such "switch" mode function or option that can be set in the PCIe IP.




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