Can the altera_pll version 18.0 be used on Cyclone V without the RREF_TL pin connected?

[LHøi0]

We are using a 5CEBA2F17C8N, 60 MHz input clock, PLL output clock also 60 MHz, feedback mode is "normal". After an IP upgrade the PLL stopped running. The upgraded PLL IP version was 18.1. Copying all the pll design files from an older project (IP TOOL version 18.0) it works again. While searching for the fault someone also discovered that the RREF_TL pin had been left unconnected in the PCB design. This will be corrected in the next hardware version, but right now we already have boards operating at customers and would like to know:

• What exactly is the function of RREF_TL pin?
• Is the 2Kohm resistor necessary for stable operation of PLL ? We are not using any transceiver channels.
• ...Or would it in this case be better to drive the internal clock network directly from the input clock pin?

[LHøi0]

And just to be clear, it *seems* to work with altera_pll ver. 18.0

[Rahul_S_Intel1]

Hi ,

Kindly find the explanation for the above.

What exactly is the function of RREF_TL pin?

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. 

Reference :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf

Use the above recommendation >> to connect 2Kohm resistor necessary for stable operation of PLL ? We are not using any transceiver channels.

[Rahul_S_Intel1]

Hi ,

Kindly let me know, if you need further assistance.

[S_Healthineers]

I have the same problem and am working with version 18.1. Now I'm waiting for the new boards where the forgotten pin RREF has been adjusted.

If I understand that correctly, if I use version 18.0, the problem is not there and then I have no problems with the PLL that do not lock.

[Rahul_S_Intel1]

Hi ,

If the issue is not there in Quartus 18.0std , requesting to use the 18.0Std.

[Rahul_S_Intel1]

Hi ,

Let me know if you need any assistance from myside