Clock Data Recovery Stratix V (time needed)

[Altera_Forum]

Good evening, 

 I want to know how much time is needed to lock the Clock Data Recovery (CDR) circuit. I am working on a project in which: 1) the data rate is 10Gbps  2) works with TDMA operation 3) in each slot the data to each receiver may come from a different trasmitter ( via optical switches) 4) receivers probably have to be like on the OLTs of the PON(burst mode receivers).  In this documnet https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/po/ss-ngpon-solutions.pdf  altera provides a solution for the PON's OLT on a Stratix V. As i understand the CDR unit has to lock in nanoseconds in order to satusfy the burst mode receivers's conditions.   But in the documents about the Stratix V, the transceivers of Stratix V and the Altera Transceiver PHY IP Core User i can't find anything about burst mode clock data recovery.  The only thing i found about time was that you have to wait 4 us after the CDR locks to data (i.e. rx_set_locktodata ='1')  before the operation of your logic begins.  I need to determine the time needed to achieve the clock data recovery because it has to be a really small part of the slot. Can anyone help?  Thank you for your time.

[Altera_Forum]

Hi, 

 As per the device datasheet, minimum time required for the CDR to lock to data after the rx_is_lockedtodata signal goes high is 4us. You may refer to Table 23. Transceiver Specifications for Stratix V GX and GS Devices of the SV device datasheet for further details.   I believe the OLT solution provided by Altera might have some custom logic to enable fast locking. You might need to contact Altera on this.

[Altera_Forum]

By the way, the following is the link to the SV device datasheet for your reference: 

 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/stratix-v/stx5_53001.pdf

[Altera_Forum]

Thanks for your answers.

[Altera_Forum]

--- Quote Start ---  Thanks for your answers.  --- Quote End ---    You are welcome. Hopefully the answers will be helpful.

[Altera_Forum]

Hi John. I am actually working on a project almost exactly the same as the one you described in the original post. Have you found any more answers? I have been playing around with resetting the RX reset controller in manual reset mode and measuring the time it takes in clock cycles to begin clocking in valid data. I am getting times much greater than 4 uS (nearly 100 uS!!). Perhaps resetting the entire PMA and PCS is not the correct way to measure the dynamic CDR synchronization time... Also, I believe that the burst mode receivers in OLTs require the ONUs to use the recovered clock as their reference clock for then transmitting data back to the OLTs. This is what allows for the nanosecond scale CDR time, because now all the CDR must do is detect the phase of the incoming data.