Cyclone IV GX SDI Multi-instances Reference

[JLee25]

Hi,

I am working on Cyclone IV GX, for multi-instances on Triple Rate SDI.

Now I found reference design on loop out, that's fine.

But I need multi-instances on my project.

Do you have any data on how to ?

Thank you!

Regards,

Johnson

[CheePin_C_Intel]

Hi Johnson, As I understand it, you have some inquiries related to using Triple Rate SDI in CIV GX devices. Sorry as I am not very clear about your specific inquiry. Just wonder if you are referring to how to create multiple instance of TR SDI IP in your design? If yes, as I understand it, each instance of the TR SDI IP only support one channel. You will need duplicate/create multiple instances for every channel that you would required. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[JLee25]

Hi Chee Pin,

Thanks for getting back.

My question is about multi-instance TR SDI, especially reconfiguration.

The project needs 2 instances and each can work independently, 2 sets TR SDI Rx/ Tx, both channels can operate at different rate.

Target device is "EP4CGX30CF23C7",

And I instantiate 2 SDI Rx and 1 SDI Tx all at Triple Rate.

If all the SDIs feed the same clock source, then full compilation is passed.

But once I add another clock as source for Rx, Quartus complaint about not able to fit into the device.

As I realized, this device has 2 MPLL on left block which could be used for transceiver.

Any idea about how I could overcome this problem?

Thank you!

Regards,

Johnson

[CheePin_C_Intel]

Hi Johnson, Thanks for your update. As I understand it, you are observing Fitter error when you try to use different refclks for the SDI RX instances. Just would like to check with you in your initial design which passed compilation, how many MPLL has been used? You may check with the Fitter report to see if both of the MPLLs have been utilized even when you are using single refclk for 2 RX and 1 TX? Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[JLee25]

Hi Chee Pin,

1 MPLL has been used in 2Rx and 1Tx, PLL_5.

Also the SDI Tx uses a GPLL, PLL_1.

There's only 1 PLL left in the design.

The clock pin was M11/ N11 for this.

I have another clock locates at M7/ N7.

But can't be used in fitter.

FYI!

BRs,

Johnson

[CheePin_C_Intel]

Hi Johnson, To facilitate further debugging, would you mind to share a simple test design which could replicate you observation? I would like to perform replication on my side for further debugging. Please let me know the specific Quartus version that you are using as well. thank you.

[JLee25]

Hi Chee Pin, Please forward to attached QAR. It’s the project I am working on. As you can see, the fitter will failed for PLL issue as mentioned. I am using Quartus Prime 17.1.0 Build 590, standard edition. FYI! Best Regards, Johnson Lee Engineering Manager Apantac LLC E: <mailto:johnson.lee@apantac.com> johnson.lee@apantac.com 7470 SW Bridgeport Road Portland, OR 97224 USA 4F.-1, No. <https://maps.google.com/?q=31,+Xintai+Rd.,**+*Zhubei+City,+Hsinchu+County+302,+Taiwan*&entry=gmail&source=g> 31, XinTai Rd., <https://maps.google.com/?q=31,+Xintai+Rd.,**+*Zhubei+City,+Hsinchu+County+302,+Taiwan*&entry=gmail&source=g> ZhuBei City, HsinChu County 302, Taiwan T: 886-3-6566-900 #502 www.apantac.com

[CheePin_C_Intel]

Hi Johnson, Sorry as I am unable to locate the QAR attached to the case. Just wonder if you would like me to drop you an email so that you could forward me the QAR? Thank you.

[JLee25]

Hi CP,

Yes, please!

Johnson

[CheePin_C_Intel]

Hi Johnson, Thanks for your design. I have responded to you in email with a example design.

[JLee25]

Hi CP,

Thanks for the share.

I would like to know further about the real application.

2 instances of TR SDI, each will operate loop out the input data independently..

How many PLL is required, MPLL/ GPLL ?

Regards,

Johnson

[CheePin_C_Intel]

Hi Johnson, For your information, I have responded to your latest email on your latest design inquiries.