I'm putting together a 2 channel transceiver design on a cyclone V GX device. This device has 3 channels. I want to use channel 1 and 3 since the custom board has already been designed and wired to these channels. All 3 channels are on the same bank in this device. Can I use IP wizard and generate a channel with its PLL. After that is done, can I simply instantiate the generated IP second time and wire it up to the dedicated pins? Will my approach work? Or do I need to create a 2 channel IP?
As I understand it, you have some inquiries related to the CV GX XCVR. From your description, I understand that your selected device has 3 XCVR channels. If I understand it correctly, you are trying to instantiate two separate PHY instance and fit into the 3 XCVR channels. Before we proceed, mind sharing on what is the specific PHY IP that you are using and also the TX PLL used? This would be helpful for me to provide further comment. For example, if you are using CMU PLL, you would need to ensure TX PLL merging to successfully fit into the 3 CHs.
I'm using Cyclone V XCVR Native PHY (altera_xcvr_native_cv). It's configured as x1 bonding with 1 data channel. PLL type is set to CMU with x1 clock network. I'm not sure how to do TX PLL merging. In fact I'm assuming that this is my problem. I have 2 instances of this IP in my design.
I also have an instance of altera_xcvr_reset_control. This IP is configured to reset 2 xcvr channels and 2 TX PLLs.
And lastly I also have an instance of alt_xcvr_reconfig. Number of reconfiguration interface is set to 2 and I've set grouping to 1,1.