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DDR3 SDRAM Controller with UNIPHY pll_ref_clk input and streaming data

Altera_Forum
Honored Contributor II
899 Views

Hi, 

 

I am trying to feed a DDR3 SDRAM Controller with UNIPHY pll_ref_clk input using a pll.  

 

I have generated the DDR3 SDRAM Controller in qsys and currently have it working with an external Oscillator feeding a FPGA Pin which is then applied to the pll_ref_clk input. I would like to feed it with a PLL instead. I am running into problems when compiling the project: 

 

ERROR: ...._p0_pin_map.tcl : Failed to find PLL reference clock 

 

This is a known issue:  

 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05282014_665.html 

 

The workaround/fix says to edit the <variation_name>_p0_get_input_clk_id procedure in the <variation_name>_p0_pin_map.tcl file and change the value from 9 to a larger value, e.g. 20 and then recompile. However when I look in this file and in this procedure I cant find the value to change!! Can anyone help me apply the workaround? 

 

On the same topic do I need to change anything in the PLL I am using to make it compatible for example setting the cascade output of the pll? 

 

Thanks 

 

James
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1 Reply
Altera_Forum
Honored Contributor II
104 Views

 

--- Quote Start ---  

Hi, 

 

I am trying to feed a DDR3 SDRAM Controller with UNIPHY pll_ref_clk input using a pll.  

 

I have generated the DDR3 SDRAM Controller in qsys and currently have it working with an external Oscillator feeding a FPGA Pin which is then applied to the pll_ref_clk input. I would like to feed it with a PLL instead. I am running into problems when compiling the project: 

 

ERROR: ...._p0_pin_map.tcl : Failed to find PLL reference clock 

 

This is a known issue:  

 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05282014_665.html 

 

The workaround/fix says to edit the <variation_name>_p0_get_input_clk_id procedure in the <variation_name>_p0_pin_map.tcl file and change the value from 9 to a larger value, e.g. 20 and then recompile. However when I look in this file and in this procedure I cant find the value to change!! Can anyone help me apply the workaround? 

 

On the same topic do I need to change anything in the PLL I am using to make it compatible for example setting the cascade output of the pll? 

 

Thanks 

 

James 

--- Quote End ---  

 

 

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