DMA without nios

[Altera_Forum]

i am thinking that how to use a dma without nios.  

it seems i shoud write a dma controller by myself.   does any one has done the same thing before?   or any one can provide me some examples?   thanks

[Altera_Forum]

Do you mean you have a system without any CPU and need to transfer data to/from memory? What's the actual use of such a system? 

You can either write your own DMA, or create a component that's able to control the registers of an existing DMA.

[Altera_Forum]

i just want to get datas form ssram throug dma,btw,that just is a homework. 

 so, now i am thinking can i use spoc-builder to generate one.

[Altera_Forum]

Yes SOPC builder is the way to go. But how will you put the data into your ssram in the first place?

[Altera_Forum]

:)i just load a image into ssram(de2-70 board through panel-tool) , i want get datas out ,then i think of dma ,meantime i saw a paper in the internet,it uses this mather throug dma do the same thing and also shows a module image without source code (those in/outputs are belowe ) . but in the paper it seems the dma module is writed by hand and made by fifo megawizard ,so i wonder if i can make one by sopc builder , aha...:), just a weird idea . 

   iCLK iFIFO_RST_n iRD1_FIFO_RD_CLK iRD1_FIFO_RD_REQ iRD2_FIFO_RD_CLK iRD2_FIFO_RD_REQ iRD3_FIFO_RD_CLK iRD3_FIFO_RD_REQ iRD4_FIFO_RD_CLK iRD4_FIFO_RD_REQ iRD5_FIFO_RD_CLK iRD5_FIFO_RD_REQ iRST_n iTRIGGER iWR1_FIFO_WR_CLK iWR1_FIFO_WR_REQ iWR1_FIFO_DATA_IN[31..0] iSSRAM_READDATA[31..0]  oRD1_FIFO_RD_EMPTY oRD2_FIFO_RD_EMPTY oRD3_FIFO_RD_EMPTY oRD4_FIFO_RD_EMPTY oRD5_FIFO_RD_EMPTY oSSRAM_READ oSSRAM_WRITE oRD1_FIFO_DATA_OUT[31..0] oRD2_FIFO_DATA_OUT[31..0] oRD3_FIFO_DATA_OUT[31..0] oRD4_FIFO_DATA_OUT[31..0] oRD5_FIFO_DATA_OUT[31..0] oSSRAM_ADDRESS[18..0] oSSRAM_WRITEDATA[31..0]

[Altera_Forum]

I don't know how the panel tool works, but you'll probably need a SOPC project with either a Nios CPU or a jtag-to-avalon debug module for it to access the SRAM. So in this case you'd better use SOPC builder and make a component with an Avalon master interface, to be able to share the SRAM between JTAG and your DMA.

[Altera_Forum]

well.. this is a stupid question, but i wanna ask anyway..  

 So you could actually create something using SOPC without implementing a NIOS 2 processor? I thought the whole purpose of using SOPC is to implement a design with a NIOS 2?  Michael

[Altera_Forum]

--- Quote Start ---  well.. this is a stupid question, but i wanna ask anyway..   So you could actually create something using SOPC without implementing a NIOS 2 processor? I thought the whole purpose of using SOPC is to implement a design with a NIOS 2?   --- Quote End ---    Its not a stupid question. All the documentation relating to SOPC/Qsys generally talk about NIOS II systems. However, all you really need is an Avalon-MM bus master. The NIOS II just happens to be one type of master.  I rarely use the NIOS II processor. I use the JTAG-to-Avalon-MM bridge for debugging, and then have other processor-to-Avalon-MM master designs for accessing components inside the FPGA.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  well.. this is a stupid question, but i wanna ask anyway..   So you could actually create something using SOPC without implementing a NIOS 2 processor? I thought the whole purpose of using SOPC is to implement a design with a NIOS 2?  Michael  --- Quote End ---    The next generation tool called "Qsys" was specifically named that to try to break the perception that you can't use SOPC Builder without Nios II. Nios II is a software core processor, SOPC Builder and Qsys are system integration tools. The only thing the SOPC Builder/Qsys have in common in common with Nios II is support for Avalon memory mapped interfaces.