FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

DSP IP problem

Honored Contributor II



I am trying to simulate a low pass filter using DSP megafunction in Modelsim. 


I am also using licensed Quartus full version to generate the IP. 


The error I am getting is: 

instantiation of 'lpf_1_ast' failed. the design unit was not found. 

# region: /test_lpf/inst 



Now, I am working in verilog i.e, the main instantiation file is "lpf_1.v". 

I have seen that FIR filter IP generates many files including "lpf_1_ast.vhd" but not "lpf_1_ast.v". 


Kindly, tell me how can I solve the problem ? 


A quick reply will be greatly appreciated. 


Thank you !!!
0 Kudos
1 Reply
Honored Contributor II



I have also tried to compile the LPF_1_ast.vhd file, it is showing the error: 

error:library auk_dspip_lib not found. 


I have tried to search the library but could not find it. 


After I synthesized the module in Quartus, by looking at the netlist viewer, it seems that the LPF_1 has got generated properly. 


Thank you !!