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Altera_Forum
Honored Contributor I
741 Views

DSP IP problem

Hi, 

 

I am trying to simulate a low pass filter using DSP megafunction in Modelsim. 

 

I am also using licensed Quartus full version to generate the IP. 

 

The error I am getting is: 

instantiation of 'lpf_1_ast' failed. the design unit was not found. 

# region: /test_lpf/inst 

 

 

Now, I am working in verilog i.e, the main instantiation file is "lpf_1.v". 

I have seen that FIR filter IP generates many files including "lpf_1_ast.vhd" but not "lpf_1_ast.v". 

 

Kindly, tell me how can I solve the problem ? 

 

A quick reply will be greatly appreciated. 

 

Thank you !!!
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1 Reply
Altera_Forum
Honored Contributor I
36 Views

Hi, 

 

I have also tried to compile the LPF_1_ast.vhd file, it is showing the error: 

error:library auk_dspip_lib not found. 

 

I have tried to search the library but could not find it. 

 

After I synthesized the module in Quartus, by looking at the netlist viewer, it seems that the LPF_1 has got generated properly. 

 

Thank you !!
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