FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Downloading ELF Process failed with DDR2 Uniphy IP

Honored Contributor II

I'm trying to use the D5M camera and an LTM LCD touch screen connected to DE4 board using Altera VIP open core. The block diagram of my design is described in the attached picture. As I don't need any runtime control, the 800x600 D5M RGB pixel data(which is the output of D5M custom IP) is used as the source of Clocked Video In IP core, followed by Frame Buffer which write pixel data into DDR and retrieve them from DDR, Clipper which generate the 800x480 to suite the LCD and Clocked Video Out, the 800X640 RGB output is directly connect with LCD. 


As I don't need any runtime control, none of the IP core is connected with avalon bus, When I downloaded the design onto the board, there are data on the LCD but they are not synchronized at all. My DDR clock is set to 400Mhz and other nios2 components uses 200MHz as system clock. I'm posting my Qsys system and the top module of my design, could any on take a look at it and tell me what could probably the problem be? Thank you very much.
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