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Dual standard SDI IP core

Honored Contributor II




I am trying to implement dual standard SDI reciver in Altera Cyclone IV (F485) EP4CGX30CF23 device. 





1. Need 4 dual standart SDI reciver in one QUAD. 

2. Each should be intepentanlly configured for SD and HD mode. 

3. Have a external clock of 148.5Mhz. 

4. having Cyclone Device with internal clock divider in CDR unit. 





We I try to instantiate the dual standard IP , I am not see any option for multiple reciver channed. 

I can see only starting channed selection. 



I even thought of making 4 seperate megacore function ip with startingchannel 2,4,6,8.  



Since for the Dual standard I need to have dynamic channel reconfiguration(enable and disable clk divider) for the tranciver channed. 

But the probleun is each instant of dual standard SDI fucction is having  

"sdi_reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);" 

"sdi_reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);" configration signals. 



Can i implement a MUX in user logic so that i can commect the reconfiguration bolck to the respective channel as required. 



Please help in to provide a solution for this. 





Another pint is the thet dual standard SDI Altera IP is a fully free ip or is that only for evaluation
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Honored Contributor II

If you need 4 dual standard receivers, you may instantiate 4 dual standard SDI IP. 

Each one must have an unique starting channel number. 

So you may use 0, 4, 8, and 16. 


For the dynamic channel reconfiguration, you can study an example in the folder "Your quartus ii installed folder\version\ip\altera\sdi\example".
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