Dynamically Switching the lane number for Displayport using Displayport IP

[HBhat2]

Hi,

I am targeting Arria 10 FPGA with Displayport IP. My Display-port Interface is with Type-C connectors ALT mode (not using Standard DP connector). When I use Type-C connector, we can have Flip connection / orientation and normal orientation. When we have the flip orientation, Lane-0 will become Lane-3, & Lane-1 will become Lane-2 and vice versa.

So, my question is whether is it possible to handle the lane swapping inside FPGA?

I referred to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dp-de.pdf document.

Page 23, Table 12, TX PHY Top  there is a note:

Note: You must set the TX channel bonding mode to PMA and PCS bonding and the PCS TX Channel bonding master parameter to 0 (default is auto).

Whether this note has any concern on swapping the Lanes dynamically ?

With Regards,

HPB

[Deshi_Intel]

Hi HPB,

It's possible to perform lane swapping but it's not done automatically.

Meaning user needs to manually manipulate the mapping on "tx_parallel_data" and "rx_parallel_data" connection between DP IP and NativePHY IP.

You can take a look on the same design example doc (page 10, page 11) where the design example use special parameter to control the different lane connection between different Bitec daughter card.

Thanks.

Regards,

dlim

[HBhat2]

Hi @DeshiL_Intel​ ,

Yes, I am aware that statically we can swap the lanes since we can assign the pin outs based on the hardware lane configuration.

In the Displayport IP user guide, page 92, Figure 29. Source Clock Tree 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf

I can see that SYNC submodule of Encoder is going to interface to Transceiver Channel HSSIO0/1/2/3. If I write a custom logic ( data mux) to swap lane-0 data to Lane-4, lane-1 data to lane-2 and vice versa, based on Type-C cable orientation, whether the design will work properly?

Whether the Master channel concept wrt Transmit Bonding will have any effect on this dynamic switching?

With Regards,

HPB

[Deshi_Intel]

Hi HPB,

My earlier suggestion is to swap tx_parallel_data and rx_parallel_data, the data bus that connect HSSI channel and DP IP together.

From DP IP perspective, by right it won't notice any lane swap effect at all as the lane swap is only happening on board.

I visualize the connection like below, DP RX lane 0 SYNC block should still works as it's interacting with data from lane 0 only all the while. Correct me if I am wrong

• DP TX (lane 0) <-> NativePHY TX (lane 4) <-> DP cable TX (lane 4)
• DP cable RX (lane 4) <-> NativePHY RX (lane 4) <-> DP RX (lane 0 SYNC)

Thanks.

Regards,

dlim

[HBhat2]

Hi,

DP is a 4 lane or 2 lane protocol. To support this we need to enable Bonding in Native PHY IP. There, we are going to mention the master channel. My first concern is if we mention channel 0 is the PCS master, and then the lane swap happens, whether that will create any problem.

Regarding Dynamic Muxing,

Consider Transceiver A -Channel 0- TX is considered as Lane-0 during compile time. and Channel-1 is Lane-1 and so on..

Once FPGA is configured and when I connect DP Sink, then consider it is a non-flip connection, So, Lane-0 of FPGA is connected to Lane-0 of DP sink, Lane-1 of FPGA is connected to Lane-1 of sink and so on..

Now, I connected a 2nd DP sink but with flip connection. With some mechanism I came to know that Type-C is in flip orientation. Now, I must send lane-4 data in channel 0 of Transceiver, Lane-3 data in channel 1, Lane-2 data in channel 2 and Lane-0 data in channel 3

So, to support this I will mux the data coming from the DP Encoder.

The data mux requirement is shown in the attached snapshot.

With Regards,

HPB

[Deshi_Intel]

Hi HPB,

Sorry for the delay in respond as I am quite tie up last week.

Now I understand better your concern on PMA and PCS bonding master channel selection. 4 lanes protocol should be fine but 2 lanes protocol is a challenge in flip orientation condition.

DP example design recommend to set lane 0 as master bonding channel for ease of channel placement management. master channel lane 0 will fit just fine for both 2 lanes and 4 lanes protocol

• 4 lanes protocol : lane 0 (master) + lane 1 (slave) + lane 2 (slave) + lane 3 (slave)
• 2 lanes protocol : lane 0 (master) + lane 1 (slave)

But now if I understand you correctly, type-C connector will flip the channel orientation to using lane 2 and lane 3 for 2 lanes protocol ?

• Meaning lane 0 and lane 1 becomes unused.
• If NativePHY still configure lane 0 as master channel while actual data traffic go through lane 3 and lane 4 then the functionality will fail.

This type-C connector flip really complicated everything

• Other than our previous discussion talked about adding mux to re-route the data traffic between transceiver channel and DP sink but now looks like you need to dynamic reconfigure transceiver channel bonding master channel selection as well to make it to work for 2 lanes protocol , right ?

You are our first customer asking about type-C connector support so I can only try my best to analyze the situation together with you.

• In short, for flip condition
• first of all, You need to have some mechanism to be able to detect the channel is already flip
• Second, you need to reconfigure transceiver channel + switch data muxing logic

Is my understanding correct ? I believed this is the reason you are asking about bonding master channel question in the first place ?

Thanks.

Regards,

dlim

[HBhat2]

Hi @DeshiL_Intel​ ,

Thanks for your in detail analysis.

" 

But now if I understand you correctly, type-C connector will flip the channel orientation to using lane 2 and lane 3 for 2 lanes protocol ?

Meaning lane 0 and lane 1 becomes unused.

"

Yes, this happens during 2-lane DP mode. otherwise (4-lane DP) During Flip, Lane-0 will become Lane-3, Lane-1 will become lane-2 and vice versa. (All channels will be used both in flip & no flip mode.

"

If NativePHY still configure lane 0 as master channel while actual data traffic go through lane 3 and lane 4 then the functionality will fail.

"

Ok, to have the proper data we need to dynamically reroute the data stream from DP encoder to corresponding PMA/native phy instances (as shown in the snapshot with previous reply)

"

Other than our previous discussion talked about adding mux to re-route the data traffic between transceiver channel and DP sink but now looks like you need to dynamic reconfigure transceiver channel bonding master channel selection as well to make it to work for 2 lanes protocol , right ?

"

Yes, this is what I want to know whether I can change the master PCS channel dynamically (using dynamic reconfiguration).

"

You are our first customer asking about type-C connector support so I can only try my best to analyze the situation together with you.

• In short, for flip condition
• first of all, You need to have some mechanism to be able to detect the channel is already flip

"

We have external logic / additional circuit to detect the flip condition or normal (no flip condition)

"

• Second, you need to reconfigure transceiver channel + switch data muxing logic

I believed this is the reason you are asking about bonding master channel question in the first place ?

"

Yes.

So, I need to see how we can change the master PCS channel in dynamic reconfiguration.

If you have came across any reference design or any material reference to change the master PCS channel through dynamic reconfiguration, please share with me.

With Regards,

HPB

[Deshi_Intel]

Hi HPB,

I am not sure what's the register control for bonding master setting but I believe the easiest way is to use dynamic reconfig streamer mif file to switch between different NativePHY IP profile setting without the need to know register control access for certain setting. For instance :

• Save NativePHY IP profile 0 with - bonding master channel set to channel xxx
• Save NativePHY IP profile 1 with - bonding master channel set to channel yyy

I don't really have exact reference design but below sim test bench design will give you an idea how the streamer profile switching works. (checkout line 155 onwards)

Profile switching reconfig flow summary as below :

1. Request access to reconfig bus via reg offset address 0x000
2. perform NativePHY profile switching via reg offset address 0x340
3. perform transceiver channel re-calibration after profile switching via reg offset address 0x000
4. Release back reconfig bus control access via reg offset address 0x000

You can also refer to A10 XCVR PHY user guide doc (chapter 6.10, page 528) to learn more about dynamic reconfig process flow

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

You can also find the A10 XCVR PHY reg mapping table in below link

• https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/xcvr-phy-support.html
• Goto left "debug" panel -> transceiver register mapping guide

Thanks.

Regards,

dlim

[HBhat2]

Hi @DeshiL_Intel​ ,

Setting different profile could ease the reconfiguration. Thanks for the suggestion & reference links. I will go through them.

Thanks!

With Regards,

HPB

[Deshi_Intel]

You are welcome !

[Deshi_Intel]

Hi HPB,

I hope you are doing well with your project development.

For now, I am setting this case to closure.

Feel free to file new forum thread for new enquiry in future.

Thanks.

Regards,

dlim