EMIF core clock sharing problem

Altera_Forum · ‎06-22-2017

Hi,

I'm trying to connect two EMIF QDRII controlers with shared clock on arria 10 (hard PHY and Soft Controller). I had generated EMIF slave component and connected it "clks_sharing_slave_in" to EMIF master "clks_sharing_master_out" (EMIFs handbook page 161 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/external-memory/emi_ip.pdf). Slave EMIFs doesnt have pll_ref_clk port, but during compilation i have an error(QDRIIA is master, QDRIIB is slave):

Error (16301): IOPLL reference clock is not connected to a clock pin

what i am missing?

Best regards,

Lukas Krupa

Altera_Forum · ‎06-22-2017

The documentation is confusing. This paragraph at the bottom of page 161 says that core clock sharing "necessitates" PLL reference clock sharing:

"Core clock sharing necessitates PLL reference clock sharing; therefore, only the

master interface exposes an input port for the PLL reference clock. All slave interfaces

use the same PLL reference clock signal."

And this section near the top of page 161 that describes PLL reference clock sharing says this:

"To implement PLL reference clock sharing, open your RTL and connect the PLL

reference clock signal at your design's top-level to the PLL reference clock port of

multiple interfaces."

So if core clock sharing "necessitates" PLL reference clock sharing then why do the slaves not expose the reference clock port? From the error message it seems pretty clear that the slaves do need a reference clock. I recommend opening a service request with Intel to get some clarification. Or maybe you'll get lucky and get a response here.

Altera_Forum · ‎06-22-2017

The confusion here is between the external reference clock and the core clock used for the multiple interfaces. First of all, I'm assuming the two interfaces are in the same I/O column and placed adjacent to each other. Indeed, the external reference clock, must be connected to both interfaces in your RTL. If the interfaces are not adjacent to each other or if intermediate banks are used for extra EMIF lanes or address/control logic, the reference clock will automatically be connected to these intermediate banks.

It sounds like you've set up the core clock master/slave connections correctly, so the issue may be that the two interfaces are not in the same column or that you've put something that uses a different clock in an intermediate I/O bank.

Altera_Forum · ‎11-06-2017

In the newer QII version like 17.0. Once you turn on the core clock option, it will disable the pll_ref_clk pin for slave component. This mean the pll_ref_clk also will connect internally through the mater-slave connection. So, you will not see this type of conflict anymore.

(This message was posted on behalf of Intel Corporation)