EMIF - ref_clk from a bank other than address control and share that ref clock for 2 EMIF instances

[BKB]

Hi,

I am using a  Stratix 10 1SG10MHN3F74C2LG dual die FPGA on our board. Each die has two EMIF instances. Each EMIF instance uses reference clock fed from the clk pins in the address control IO Bank.

FPGA - Stratix 10 1SG10MHN3F74C2LG

Below are the current banks for each EMIF instance and their reference clock pins.

Die U1 - EMIF 1 uses IO bank 2LU1, 2MU1, 2NU1 with ref_clk in bank 2MU1 at pins AC69 and AB69

Die U1 - EMIF 2 uses IO bank 2GU1, 2HU1, 2IU1 with ref_clk in bank 2MU1 at pins AV55 and AW55

Die U2 - EMIF 3 uses IO bank 2HU2, 2IU2, 2JU2 with ref_clk in bank 2IU2 at pins AW15 and AV15

Die U2 - EMIF 4 uses IO bank 2LU2, 2MU2, 2NU2 with ref_clk in bank 2MU2 at pins BM1 and BL1

Instead of the reference clock as mentioned above for each EMIF instance, I want to to use reference clock in some other bank in each die and share it between two EMIF in that die.

Below is the bank and pin number for the reference clock from the each die

Die U1 - Bank 2KU1 - pins AK67 and AK68

Die U2 - Bank 3DU2 - pins T25 and U25

Please let me know if we can replace the existing reference clocks with the reference clock from other bank for each die and use the same reference for both the EMIF instances. If this is possible, how can it be done.

Best,

Bharat

[sstrell]

Have you tried using Interface Planner in Quartus to see if this is possible?  That would be the easiest way to see without having to wait for a full compilation.

[BKB]

I had tried implementation with the pinout as desired and it did nor work. Hence I had posted here if there was a workaround.
I did try the interface planner after your suggestion and got the errors there too.

If there was a way to to make it work, as I had described in the original post. please let me know.

Best,

Bharat

[AdzimZM_Intel]

Hi Bharat,

The User Guide has some guidelines when sharing the PLL Reference Clock between multiple EMIF interfaces.

Here is the link to User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683741/24-1-19-2-8/resource-sharing-guidelines-multiple-01.html

Based on the User Guide, you should place the ref_clk in Address/Command group, in the same column and the EMIF IP should has similar frequency.

You need to choose a different pin location for ref_clk that located within the Address/Command group.

You also need to connect the same signal in RTL code.

Regards,

Adzim

[BKB]

Thanks Adzim. I went through that. I was hoping if there was a way to connect a clock from a different bank but there isn't.

Thanks again.

Best,

Bharat

[AdzimZM_Intel · Accepted solution]

Hi Bharat,

Unfortunately, the ref_clk need to be placed within the Address and Command group.

Sharing the pin to other EMIF IP is permitted but need to follow the rules.

Regards,

Adzim

[BKB]

Thanks Adzim,

Best, Bharat