In Cyclone 10 Gx FPGA how do I make sure that the HDL synchronizer design will synthesize using Static flip-flops instead of dynamic flip-flops? By Static flip-flop I am referring to flip-flop that has regenerative design at the back-end. Perhaps this FPGA has no static flip-flop anyhow? I look forward to your feedback. Thank you
Are referring to this type of static and dynamic flip flop? in the below below.
How did you determine in Quartus the HDL synchronizer is using the dynamic flip flop? Is it some configs in there in the QP regarding this?
Please see the following link for description on Dynamic Flip-flop
I do not know of any option within Quartus to choose the type of FF and therefore I posted the original question wondering if I can constrain on FFs so that only static FFs are chosen for synchronizer design.
No, there are not different kinds of flip-flops like this. The Quartus Prime software can identify synchronizer chains and place and route the registers to maximize MTBF. Some online trainings that might be helpful:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1113.html (older but might still be relevant to your question)
The setting in Quartus: