Ethernet IP Core

[Altera_Forum]

Hi, 

 I would like to ask You the next question.  The sending process to Avalon Bus controlled by ff_tx_sop and ff_tx_eop signals (in addition to other signals). In order to send user's data, Have I build the full frame includes destination address, preambula, source address, type of message etc. or I need to provide data I interested to send only (Full frame is build by the the MAC MegaWizard automatically)  In case of automatic frame building, where have I to enter the source address?  In other words, what kind of data have I to provide to ff_tx_data between "start of packet" and "end of packet" signals.  Thanks

[Altera_Forum]

You have to build the full frame. This is described in Table 7-8 of the user guide (ug_ethernet.pdf) [among other places] 

   --- Quote Start ---   ff_tx_sop - startofpacket - Transmit start of packet. Assert this signal when the first byte in the frame (the first byte of the destination address) is driven on ff_tx_data.   --- Quote End ---     --- Quote Start ---   ff_tx_eop - endofpacket - Transmit end of packet. Assert this signal when the last byte in the frame (the last byte of the FCS field) is driven on ff_tx_data.   --- Quote End ---  

[Altera_Forum]

Thanks for quick reply! 

 And what about "Preamble" and "SFD"? Added by the Core automatically?   I have to provide the FCS ? As I know, the calculation can be done by the Core.  Tnx,  Yevgeny

[Altera_Forum]

--- Quote Start ---   And what about "Preamble" and "SFD"? Added by the Core automatically?    --- Quote End ---    Yes.    --- Quote Start ---   I have to provide the FCS ? As I know, the calculation can be done by the Core.   --- Quote End ---    I believe whether or not to include it depends on how you have configured the core. If you have CRC enabled, you don't include it. If you don't have CRC enabled, you do include it.

[Altera_Forum]

Thanks Ted!

[Altera_Forum]

Hi, Ted, I have one more question... 

 After deep core examination, I see that Altera provides only the most basic core with PHY interface and Error Calculation blocks only. That suggesting me P2P communication only (Physical layer of OSI Model) It doesn't support things like UDP or TCP\IP Standards. Am I wright?  Thanks  Y.

[Altera_Forum]

--- Quote Start ---  After deep core examination, I see that Altera provides only the most basic core with PHY interface and Error Calculation blocks only. That suggesting me P2P communication only (Physical layer of OSI Model) It doesn't support things like UDP or TCP\IP Standards. Am I wright?   --- Quote End ---    The Altera Triple Speed Ethernet IP Core (described in ug_ethernet.pdf) does not implement any part of UDP or TCP/IP. It is not an TCP offload engine, for example. However, nothing prevents using it as part of a system implementing those protocols similar to how you might have used a discrete MAC IC with ISA/PCI/PCIe interface years ago.  The "Simple Socket Server" NIOS example simply uses a pair of SGDMA channels to transfer the Avalon-ST Ethernet frames to/from RAM. The supplied iniche TCP/IP software stack executing on a NIOS takes care of all aspects of the Internet Protocol family.  Here are some links of systems which you might find useful to review.  http://www.altera.com/support/examples/nios2/exm-net-std-de.html  http://www.alterawiki.com/wiki/nios_ii_udp_offload_example