Hi,as described in this (http://www.alteraforum.com/forum/showthread.php?t=46963&p=193556#post193556) thread I deploy two NIOS Gen2 cores of which one is bootloaded via EPCS. Once this is up I iterate through the EPCS till I find the instructions for the second NIOS. The content of the EPCS is generated using a the following commands:
echo "$(tput setaf 1) Generating and programming SOF $(tput sgr 0)" sof2flash --input="$1/logic.sof" --output="$1/flash/logic_epcs_flash_controller.flash" --epcs --verbose nios2-flash-programmer "$1/flash/logic_epcs_flash_controller.flash" --base=0x800 --epcs --sidp=0x10000000 --id=0x4 --device=1 --instance=1 --program --verbose --erase-all echo "$(tput setaf 1) Generating and programming COM $(tput sgr 0)" elf2flash --input="$1/software/COM/COM.elf" --output="$1/flash/COM_epcs_flash_controller.flash" --epcs --after="$1/flash/logic_epcs_flash_controller.flash" --verbose nios2-flash-programmer "$1/flash/COM_epcs_flash_controller.flash" --base=0x800 --epcs --sidp=0x10000000 --id=0x4 --device=1 --instance=1 --program --verbose echo "$(tput setaf 1) Generating and programming App $(tput sgr 0)" elf2flash --input="$2" --output="$1/flash/App.flash" --epcs --after="$1/flash/COM_epcs_flash_controller.flash" --verbose nios2-flash-programmer "$1/flash/App.flash" --base=0x800 --epcs --sidp=0x10000000 --id=0x4 --device=1 --instance=1 --program --verboseI use the resetrequest and resettaken signals as described here (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an458.pdf)in the external boot flow section. But somehow the second Nios is just coming up sporadically. Funny enough, it came up before I saw the part about inserting the branch instruction at the reset address. I somehow have the feeling that it depends on the size or the alignment of the "code" or rather instructions for the second Nios. Did anyone experience the same behaviour? Any suggestions? Thanks!
For the people of the future:I - once again - stumbled over the data cache. I had to flush the data cache of the "master" NIOS after I copied the instructions from EPCS to the slave NIOSs RAM. Somehow I assumed that the EPCS functions are based upon __builtin_stwio/__builtin_ldwio. Just to clarify: I don't put the unconditional branch at the the reset vector address as described here (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an458.pdf). Just copy the various boot records from the EPCS to the according locations in RAM, flash the dcache, release the reset and the system is running. Just to mention: For timing reasons I placed a pipeline bridge between the master NIOS and some peripherals (the SDRAM of the slave). So obviously the address offset of the pipeline bridge has to be added to the memory locations extracted from the boot records.