FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

SOPC error, SLAVE at two addresses

DDR2 termination

board setting for DDR2 HP core

serial lite data rates

Sampling time and clock

ip university program error

Question on niosII UDPoffload reference design

DDR vs DDR2 performance question

IP Generator Error - DSP Builder

Frame Reader Initialization

Arria 2 DDR3 shared PLL

multichannel FIR output timing error

Ethernet transmission

web edition contains one or more time-limited megafunctions

Avalon-ST vs Descriptor/Data in pcie ip 9.1

Featured Content

UART Core IP (RS-232 Serial Port)

Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Critical Warning: PLL clock

Re: Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Re: Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Error reported by S-function 'mip_control' in Control Block

Re: Altera Simple Dual Port RAM -- Read cycle latency