FIFOed UART Qsys Generation Error with Qsys Standard v18.1

[TMK]

Hello,

when generating a FIFOed UART with Qsys Standard v18.1 as provided here

https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005RTHQA2&artTopicId=0TO0P000000MWKBWA4&action=view

I receive the following Qsys generation errors:

Info: tube_uart_0: Starting FIFOed UART Generation at C:/xy/Qsys/fifoed_uart

…

Info: tube_uart_0: Starting RTL generation for module 'f2flink_tube_uart_0'

…

Info: tube_uart_0:

Info: tube_uart_0: ERROR:

Info: tube_uart_0: no width for __0__/* synthesis keep */

Error: tube_uart_0: Failed to generate module f2flink_tube_uart_0

Info: tube_uart_0: Done RTL generation for module 'f2flink_tube_uart_0'

Info: tube_uart_0: "f2flink" instantiated fifoed_avalon_uart "tube_uart_0"

Error: Generation stopped, 15 or more modules remaining

This issue seems to be related to the Tx FIFO option (see screenshot).

Could you please let me know how this problem can be fixed and if a patch is available? Thank you.

Best regards,

Thomas

[KennyTan_Altera]

Unfortunately, nope. Usually, if the IP official support from the engineering, you will not need to downloading in the website. It will be exist in the Installed IP when you install the Quartus Prime.

However, if you wish to have this IP. What I can do is file an enhancement to our engineering to include this IP in the future release of Quartus Prime Pro.

[TMK]

So I understand that this IP never was really under support from Intel. I think that mainly customers in the low-cost field using the Quartus Prime Standard edition would benefit the most. I don't work with the Pro edition but I think that other users could benefit from it. But who knows, in a data center a UART is probably not the interface of choice.

[KennyTan_Altera]

understood, I will try to get this enhancement done on Standard as well.