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TMK
Beginner
382 Views

FIFOed UART Qsys Generation Error with Qsys Standard v18.1

Hello,

 

when generating a FIFOed UART with Qsys Standard v18.1 as provided here

 

https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005RTHQA2&artTopicId=...

 

I receive the following Qsys generation errors:

 

Info: tube_uart_0: Starting FIFOed UART Generation at C:/xy/Qsys/fifoed_uart

Info: tube_uart_0: Starting RTL generation for module 'f2flink_tube_uart_0'

Info: tube_uart_0:

Info: tube_uart_0: ERROR:

Info: tube_uart_0: no width for __0__/* synthesis keep */

Error: tube_uart_0: Failed to generate module f2flink_tube_uart_0

Info: tube_uart_0: Done RTL generation for module 'f2flink_tube_uart_0'

Info: tube_uart_0: "f2flink" instantiated fifoed_avalon_uart "tube_uart_0"

Error: Generation stopped, 15 or more modules remaining

 

This issue seems to be related to the Tx FIFO option (see screenshot).

 

Could you please let me know how this problem can be fixed and if a patch is available? Thank you.

 

Best regards,

Thomas

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23 Replies
KennyT_Intel
Moderator
37 Views

may I know what OS that you were using? I will try duplicate it and find the workaround for it.

TMK
Beginner
37 Views

I'm using Windows 7. Important information is that the problem only happens when generating VHDL (not Verilog) output and seems to be related to the synthesis directive.

KennyT_Intel
Moderator
37 Views

I try it on VHDL and verilog, it get error. Where did you generate this IP? In the IP catalog or in the platform designer?

 

This IP was created in Q13.1, at that time, it is still using megafunction (not IP catalog) and this IP does not exist in the megafucntion.

 

You have use this IP in the platform designer. I try it on verilog and vhdl, I am using redhat. No error found when generating the IP.

 

Thanks

TMK
Beginner
37 Views

Well, as mentioned earlier I generate this IP in Platform Designer, formerly Qsys. Did you copy the settings from the screenshot to reproduce the problem? Please perform the following steps to reproduce the problem:

 

  1. Create a Cyclone IV project
  2. Open Platform Designer
  3. Add a FIFOed UART instance
  4. Enable the Tx FIFO
  5. Set synthesis output to VHDL and generate the system
KennyT_Intel
Moderator
37 Views

I am using Cyclone V, have ensure the same steps above. No eror.

 

The only different that we have is I am using redhat. Do you have other computer to try out? like windows 10?

TMK
Beginner
37 Views

Why don't you use Windows 10? Could you please share the Qsys generation report and a screenshot with the IP configuration settings?

KennyT_Intel
Moderator
37 Views

I attached the screenshot, I do not have Q18.1 installed in my windows 10.

TMK
Beginner
37 Views

Thank you for the screenshots. My version is: Platform Designer 18.1 Build 625

 

Is it possible that you reproduce the problem in a Windows (7 or later) environment?

KennyT_Intel
Moderator
37 Views

I will try it in Windows 10. but will need some time on this

KennyT_Intel
Moderator
37 Views

Here is the result for windows 10.

KennyT_Intel
Moderator
37 Views

Here is the zip files that I used.

KennyT_Intel
Moderator
37 Views

any update?

TMK
Beginner
37 Views

Thank you for your update. In order to reproduce the issue you have to select "Create simulation model: VHDL" in the generation window. Could you please try that as well?

KennyT_Intel
Moderator
37 Views

Well. I had try this before. no problem found as well.

TMK
Beginner
37 Views

As I'm able to reproduce the issue with the IP core provided by you and a new test system similar to yours, could you please try it again?

TMK
Beginner
37 Views

Btw, could you check with support why I permanently fail to log in to the Intel forum and it only works when I reset my password before?

KennyT_Intel
Moderator
37 Views

You mention that you was able to reproduce the issue, are you using windows 7? As mention, I am using windows 10 and redhat. Would you able to use windows 10?

 

For reset password problem, can you file a new thread to address this differently?

TMK
Beginner
37 Views

My colleague has Windows 10 installed on his machine and is able to reproduce the problem as well. Could you please try again on Windows 10?

KennyT_Intel
Moderator
37 Views

Today I tried again and I am getting error in windows 10, seems like I might have choose the wrong language in my previous test.

 

Error: fifoed_avalon_uart_0: Failed to generate module Test_fifoed_avalon_uart_131_rxorl4y

Info: fifoed_avalon_uart_0: Done RTL generation for module 'Test_fifoed_avalon_uart_131_rxorl4y'

Error: Generation stopped, 1 or more modules remaining

Info: Test: Done "Test" with 3 modules, 1 files

Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings

 

If you swith from VHDL to verilog for simulation, the error goes away. Since modelsim able to support mixed language simulation, you will have to choose Verilog instead.

 

Please note that there will be no fixed/support for old version of IP (in your case Q13.1). We are sorry to inform that.