when generating a FIFOed UART with Qsys Standard v18.1 as provided here
I receive the following Qsys generation errors:
Info: tube_uart_0: Starting FIFOed UART Generation at C:/xy/Qsys/fifoed_uart
Info: tube_uart_0: Starting RTL generation for module 'f2flink_tube_uart_0'
Info: tube_uart_0: ERROR:
Info: tube_uart_0: no width for __0__/* synthesis keep */
Error: tube_uart_0: Failed to generate module f2flink_tube_uart_0
Info: tube_uart_0: Done RTL generation for module 'f2flink_tube_uart_0'
Info: tube_uart_0: "f2flink" instantiated fifoed_avalon_uart "tube_uart_0"
Error: Generation stopped, 15 or more modules remaining
This issue seems to be related to the Tx FIFO option (see screenshot).
Could you please let me know how this problem can be fixed and if a patch is available? Thank you.
I try it on VHDL and verilog, it get error. Where did you generate this IP? In the IP catalog or in the platform designer?
This IP was created in Q13.1, at that time, it is still using megafunction (not IP catalog) and this IP does not exist in the megafucntion.
You have use this IP in the platform designer. I try it on verilog and vhdl, I am using redhat. No error found when generating the IP.
Well, as mentioned earlier I generate this IP in Platform Designer, formerly Qsys. Did you copy the settings from the screenshot to reproduce the problem? Please perform the following steps to reproduce the problem:
I am using Cyclone V, have ensure the same steps above. No eror.
The only different that we have is I am using redhat. Do you have other computer to try out? like windows 10?
You mention that you was able to reproduce the issue, are you using windows 7? As mention, I am using windows 10 and redhat. Would you able to use windows 10?
For reset password problem, can you file a new thread to address this differently?
Today I tried again and I am getting error in windows 10, seems like I might have choose the wrong language in my previous test.
Error: fifoed_avalon_uart_0: Failed to generate module Test_fifoed_avalon_uart_131_rxorl4y
Info: fifoed_avalon_uart_0: Done RTL generation for module 'Test_fifoed_avalon_uart_131_rxorl4y'
Error: Generation stopped, 1 or more modules remaining
Info: Test: Done "Test" with 3 modules, 1 files
Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings
If you swith from VHDL to verilog for simulation, the error goes away. Since modelsim able to support mixed language simulation, you will have to choose Verilog instead.
Please note that there will be no fixed/support for old version of IP (in your case Q13.1). We are sorry to inform that.