FP_FUNCTIONS IP Pipelined?

[ArcticRain]

Trying to use the Multiply and Addition functions out of the FP_FUNCTIONS IP.  It is clear what the latency through the IP is for a given operation.   However, it isn't clear if the operations are pipelined such that I can feed inputs in on every clock cycle and expect outputs on every clock cycle the latency number of cycles later.  Anyone have any experience here that could help me understand expected operation?

[FvM]

Hello,
"However, it isn't clear if the operations are pipelined such that I can feed inputs in on every clock cycle and expect outputs on every clock cycle the latency number of cycles later. "
Yes that's how pipelining works, definitely also Intel float IP.
Regards,
Frank

[ShengN_Intel · Accepted solution]

Hi,

Yes, FP_FUNCTIONS IP is pipelined. The waveforms of FP_FUNCTIONS IP with no latency and latency of 2 are attached below for your reference.

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi,

Any further concern or consideration?

Thanks,

Best Regards,

Sheng