Generation of PCI Express Avalon ST Example

[PVanL]

I generate the PCIe ST example as described in ug_dex_pcie_avst_19_1_1. I have Quartus Pro 18.0. I selected the Cyclone10GX version: 10CX220YF780E5G, as that is the version on the development board. At tab "Board Settings", i could not select any board?!

At Design Environment / Interface views i selected "system", but do not really know what it means. Please explain. It eventually presented at "Target development board" the "Arria 10GX FPGA development kit", or the "Arria 10GX FPGA dev.kit ES2", NOT the cyclone10GX board. Please Advice. Correction: after generating the HDL, it changed the interface view from 'system' back to 'standalone'. Please advice.

In Modelsim it compiles partially. Please check the transcript below. What goes wrong?

# Top level modules:

# End time: 13:35:53 on Jun 17,2020, Elapsed time: 0:00:05

# Errors: 0, Warnings: 584

# Model Technology ModelSim - Intel FPGA Edition vcom 10.6c Compiler 2017.07 Jul 26 2017

# Start time: 13:35:54 on Jun 17,2020

# vcom -reportprogress 300 C:/intelfpga_pro/18.0/quartus/eda/sim_lib/cyclone10gx_hip_components.vhd -work cyclone10gx_hip

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling package CYCLONE10GX_HIP_COMPONENTS

# -- Compiling package body CYCLONE10GX_HIP_COMPONENTS

# -- Loading package CYCLONE10GX_HIP_COMPONENTS

# -- Compiling package TWENTYNM_HIP_COMPONENTS

# -- Compiling package body TWENTYNM_HIP_COMPONENTS

# -- Loading package TWENTYNM_HIP_COMPONENTS

# End time: 13:35:54 on Jun 17,2020, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vcom 10.6c Compiler 2017.07 Jul 26 2017

# Start time: 13:35:54 on Jun 17,2020

# vcom -reportprogress 300 C:/intelfpga_pro/18.0/quartus/eda/sim_lib/cyclone10gx_hip_atoms.vhd -work cyclone10gx_hip

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package CYCLONE10GX_HIP_COMPONENTS

# -- Compiling entity cyclone10gx_hssi_gen3_x8_pcie_hip

# -- Compiling architecture behavior of cyclone10gx_hssi_gen3_x8_pcie_hip

# -- Loading package TWENTYNM_HIP_COMPONENTS

# -- Compiling entity twentynm_hssi_gen3_x8_pcie_hip

# -- Compiling architecture behavior of twentynm_hssi_gen3_x8_pcie_hip

# End time: 13:35:54 on Jun 17,2020, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# [exec] com

# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017

# Start time: 13:35:54 on Jun 17,2020

# vlog -reportprogress 300 -sv ../../../ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv -work altera_common_sv_packages

# -- Compiling package altera_xcvr_native_a10_functions_h

#

# Top level modules:

#   --none--

# End time: 13:35:54 on Jun 17,2020, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017

# Start time: 13:35:54 on Jun 17,2020

# vlog -reportprogress 300 ../../../ip/pcie_example_design/pcie_example_design_MEM/altera_avalon_onchip_memory2_180/sim/pcie_example_design_MEM_altera_avalon_onchip_memory2_180_7oxmr5i.v -work altera_avalon_onchip_memory2_180

# ** Error: (vlog-7) Failed to open design unit file "../../../ip/pcie_example_design/pcie_example_design_MEM/altera_avalon_onchip_memory2_180/sim/pcie_example_design_MEM_altera_avalon_onchip_memory2_180_7oxmr5i.v" in read mode.

# No such file or directory. (errno = ENOENT)

# End time: 13:35:54 on Jun 17,2020, Elapsed time: 0:00:00

# Errors: 1, Warnings: 0

# C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.

[SengKok_L_Intel]

Hi,

The PCIe IP did not have the board selection of Cyclone 10 FPGA board, however, you can refer to the AN 855 to get the example design.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an855.pdf

Below is the description from the user guide about the Standalone vs System environment:

The Standalone environment refers to the IP being in a standalone state where all its interfaces are exported. • The System environment refers to the IP being instantiated in a Platform Designer system.

Regards -SK

[SengKok_L_Intel]

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