Glitch less clock

[ymiler]

Hi

I need to implement multiplexer between 2 async clocks
there is a flag that should choose between them
This code can cause to glitch clock and I'd like to avoid from it

I can't use the "clock control Intel FPGA IP" since this option doesn’t enable for my device - Stratix 10 -1SM21BHU2F53E2VG

other option is implement the following :

but , the tool report that it's unsupported cascaded clock so that tool can't convert it.

Do you idea how can I solve this issue ?

Yishay

[sstrell]

Doesn't the clock control block have an enable signal option?  Can't you use that?

[ymiler]

According to this page :

https://www.intel.com/content/www/us/en/support/programmable/articles/000076600.html

only part of the devices have this option :

Indeed , the Quratus message is :

But , I get same message in newer Quartus version 

[Nurina]

Hi,

Sorry for the late response. Can you share the .qar file here?

Regards,

Nurina

[ymiler]

sure ,

Please send me pointer to secure share location 

[ymiler]

pointer to secure and Intel Only Access.

[Nurina]

Hi,

You may share the design through email. I'll send you an email right now.

Regards,

Nurina

[Nurina]

Hi Yishay,

I suggest you use the enable signal available in the IP. Is there any reason why you cannot use this?

Regards,

Nurina

[ymiler]

Hi Nurina,

As I wrote in the top of this case I cant enable this signal since this option doent available 

Yishay

[sstrell]

We're not talking about that option.  Scroll down.  Under "Clock Gating", use the enable options there.

[ymiler]

OK ,

I see what you are taking about ,

But , how  this option can solve the glitch less issue ?

I need the switchover option :

[Nurina]

Hi,

As mentioned in this KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000076600.html

You can prevent glitches during clock switchover by using the ena port.

The ensure glitch free clock switchover option is not available in any of the Clock Control IP for Stratix 10 at the moment unfortunately, so you'll have to use clock enable : https://www.intel.com/content/www/us/en/docs/programmable/683195/20-3/ip-core-parameters-29948.html

Regards,

Nurina

[ymiler]

Hi 

Thank you 

I will use it , this is a good workaround .

Yishay

[Nurina]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey

Regards,

Nurina