FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

[HDMI IP] AVI InfoFrame

amildm
소중한 기여자 I
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Hi All,

 

The question is related to the Intel HDMI IP.

 

According to the Table 23 in the UG-HDMI 2021.06.25, the AVI InfoFrame port has 113 bits width (bit 112 is a control bit).

But, in the generated HDMI IP, the port has only 112 bits width. Why? What's missing?

 

Thanks!

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ZH_Intel
직원
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Hi Dmitry,

 

Thank you for you patience.

>But, in the generated HDMI IP, the port has only 112 bits width. Why?

Yes, you are correct, HDMI only have 112 bits width and bit 112 is a control bit.

Sometime it could be a documentation typo/update delay and it will require some time to be revised as it require approvals from the internal team before it can be released to the public. For this case, it is caused by documentation update delay.

 

Based on the latest HDMI User Guide, I believe you are talking is table 24, the AVI InfoFrame for Support FRL = 0,

The correct bit width is as you mention which is 112 bits.

 

You may refer to below link for the latest HDMI IP User Guide:

HDMI Intel® FPGA IP User Guide 

 

Thank you.

 

Best Regards,

ZulsyafiqH_Intel

 

원본 게시물의 솔루션 보기

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ZH_Intel
직원
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Hi Dmitry,


Currently we are confirming the details with our internal team.

We will get back to you as soon as possible.


Thank you.


Best Regards,

ZulsyafiqH_Intel


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ZH_Intel
직원
970 조회수

Hi Dmitry,

 

Thank you for you patience.

>But, in the generated HDMI IP, the port has only 112 bits width. Why?

Yes, you are correct, HDMI only have 112 bits width and bit 112 is a control bit.

Sometime it could be a documentation typo/update delay and it will require some time to be revised as it require approvals from the internal team before it can be released to the public. For this case, it is caused by documentation update delay.

 

Based on the latest HDMI User Guide, I believe you are talking is table 24, the AVI InfoFrame for Support FRL = 0,

The correct bit width is as you mention which is 112 bits.

 

You may refer to below link for the latest HDMI IP User Guide:

HDMI Intel® FPGA IP User Guide 

 

Thank you.

 

Best Regards,

ZulsyafiqH_Intel

 

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ZH_Intel
직원
946 조회수

Hi Dmitry,


We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.


Best Regards,

ZulsyafiqH_Intel


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