HDMI IP Data and clock settings

[RonenP]

Hi

I am trying to set the HDMI IP to work at  only one resolution of 4k 60fps on a cyclone 10 GX (i.e. HDMI 2.0).

According to the HDMI specs. the pixel clock has to be at 594MHZ with 4400 total horizontal columns and 2250 vertical lines. Yet the HDMI IP accepts 2 symbols on every clock.

The question I have is what frequency of clock I need to use and if I have to modify the resolution values in order to get the IP to operate at that resolution rate.

Any help would be appreciated

[Deshi_Intel]

Hi,

You can checkout the HDMI related clocking scheme calculation at table 14 (page 23, 24) of below C10 HDMI design example doc.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-hdmi-c10gx.pdf

Thanks.

Regards,

dlim

[RonenP]

Hi Deshi

Thank you for the quick reply.

I looked it over yet I still am confused.

In order to send 4k60fps the pixel clock should be 594Mhz based on the following resolution values :

4400 total horizontal count and 2250 total vertical count.

Yet the IP accepts 2 symbols per clock. What values do I need to modify for the horizontal, vertical and pixel clock in order to get the 4k60fps ?

Thank you for your  time

[Deshi_Intel]

HI,

HDMI IP has its own encoding and decoding logic and the HDMI example design page 23/24 is telling you the right clock frequency that you need to supply to the HDMI IP

• The most crucial clock will be the link_speed_clock (ls_clk) and video_data_clock (vid_clk)

Assume your 4k Pixel clock = HDMI TMDS clock = 594MHz

Then you can basically use the formula shown in page 23/24 to calculate required ls_clk and vid_clk

ls_clk = TMDS clock frequency/ Symbol per clock = 594/2 = 297MHz

Assume you are using 10 bit per colour with colour depth factor = 1.25

vid_clk = TMDS clock/ Symbol per clock/ Color depth factor = 594/2/1.25 = 237.6MHz

You can also checkout HDMI IP user guide doc if you would like to learn more about HDMI IP usage

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_hdmi.pdf

Thanks.

Regards,

dlim

[Deshi_Intel]

HI,

I didn't hear back further from you.

Hopefully my earlier explanation is clear to you.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim

[RonenP]

Sorry

Due to covid 19 could not reply in a timely manner.

I would like to know the following.

For a 4k 60fps the following values are used :

pixel clock : 594MHZ 

Total horizontal count : 4400 pixel clocks

Visible pixel count       : 3840

Horizontal front porch : 176

Horizontal back porch : 144

Horizontal sync             : 88

Total vertical count  : 2250 vertical lines

Visible line count      : 2160

Vertical front porch : 8

Vertical back porch : 72

Vertical sync             : 10

The IP (on Cyclone 10GX) accepts 2 pixels per clock.

what would be the correct clock frequency and count values the IP needs to receive in order to operate correctly at 4k 60 fps.

Another issue I am having is what are the infoframes values I need to set for the IP to operate at a 4k 60 fps, if at all. Does the IP need the info frames in order to output the mentioned resolution.

And last but not least I would like to know what I am suppose to see on the transceiver output of the clock signal since when connecting this line to a scope I do not see a clock signal.