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Altera_Forum
Honored Contributor I
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HPC II DDR2 problem

I found strange issue when working with HPC II in half-rate mode (Cyclone IV + Micron DDR2 chip). Local bus is 64-bit wide (four 16-bit words). Then I do read reading last 16-bit word replaced with previous. Last word appear before next local_read_req. Can anyone help?

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