FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

HPC II DDR2 problem

Altera_Forum
Honored Contributor II
794 Views

I found strange issue when working with HPC II in half-rate mode (Cyclone IV + Micron DDR2 chip). Local bus is 64-bit wide (four 16-bit words). Then I do read reading last 16-bit word replaced with previous. Last word appear before next local_read_req. Can anyone help?

0 Kudos
0 Replies
Reply