FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Hello, Using a PCIe, I am connecting a Cyclone V SoC kit with a Linux computer. lspc is showing that the width capability is X4 and the negotiated width is X2. Have you a solution to get the X4 width? Best regards

LZERI
Beginner
‎06-18-2020 04:15 PM
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EBERLAZARE_I_Intel
Employee
‎08-04-2020 01:43 PM
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Hi,

Here is the example design for Cyclone V on PCIe root port gen 1x4:

https://rocketboards.org/foswiki/Projects/A10AVCVPCIeRootPortWithMSILTS

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