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JET60200

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07-23-2020
02:59 AM

175 Views

Helllo,

I works on Intel Arria10 EVM, I really need an FFT IP example design for my A10 project? I open my Quartus pro 19.2 (platform designer) , but fail to find where to generate an example design for FFT IP Core ? Pleade advise where to generate for my starter of FFT verification .

BTW: I need to build a 4096-point FFT / IFFT project in our own board.

Appreciate help~

Accepted Solutions

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CheePin_C_Intel

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07-30-2020
02:41 AM

151 Views

Hi,

As I understand it, you have some inquiries related to Natural and Digit Reverse for the FFT output. At high level, when there is digit reverse at the FFT output, the sequence of the output samples will be re-arranged. The new sequence is determined by reversing each sample's index bits. For further information and better illustration, you can refer to the following link with examples and sample code:

https://www.mathworks.com/help/signal/ref/digitrevorder.html

Hopefully this is helpful. Thank you.

6 Replies

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JET60200

New Contributor I

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07-23-2020
05:28 AM

167 Views

Hi CheePin, nice to @ u, since I see you had answered several FFT IP related questions here.

When checking FFT IP UG : " 3.4.2.3. I/O Order " ,

Natural order |

Digit Reverse Order |

I don't understand them very well, Can you give an explaination, and any example of "Natural ordr” / " Digit reverse order " ？ I have some incorrect FFT output in A10 project, so I wantto understand where may introduce error.

Thanks in advance

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CheePin_C_Intel

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07-30-2020
02:41 AM

152 Views

Hi,

As I understand it, you have some inquiries related to Natural and Digit Reverse for the FFT output. At high level, when there is digit reverse at the FFT output, the sequence of the output samples will be re-arranged. The new sequence is determined by reversing each sample's index bits. For further information and better illustration, you can refer to the following link with examples and sample code:

https://www.mathworks.com/help/signal/ref/digitrevorder.html

Hopefully this is helpful. Thank you.

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CheePin_C_Intel

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07-31-2020
02:53 AM

143 Views

Hi,

I notice that you have another inquiry related to FFT example design generation. As a workaround, you can try to generate a simulation example design for FFT IP in older Quartus standard edition ie Q17.0. You can configure your FFT IP and then click on Generate Example Design.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

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JET60200

New Contributor I

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08-04-2020
12:23 AM

135 Views

thanks @CheePin_C_Intel，

we had addressed our issue, you can close the bug. Thanks for kindly help./

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CheePin_C_Intel

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08-04-2020
07:48 PM

126 Views

Hi,

Glad that you have managed to resolve the issue. Thank you.

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I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

CheePin_C_Intel

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08-04-2020
07:48 PM

126 Views

For more complete information about compiler optimizations, see our Optimization Notice.