FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

Hello, Using a PCIe, I am connecting a Cyclone V SoC kit with a Linux computer. lspc is showing that the width capability is X4 and the negotiated width is X2. Have you a solution to get the X4 width? Best regards

LZERI
Beginner
146 Views
 
0 Kudos
1 Reply
EBERLAZARE_I_Intel
125 Views

Hi,

Here is the example design for Cyclone V on PCIe root port gen 1x4:

https://rocketboards.org/foswiki/Projects/A10AVCVPCIeRootPortWithMSILTS

Reply