FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

How can I use Cyclone 10GX LVDS SERDES IP without PLL?

silenfax
Beginner
169 Views

Hello, I setup LVDS SERDES IP with external PLL. Can I clocking ext_fclk, ext_loaden, ext_coreclock directly without external PLL?

0 Kudos
2 Replies
EngWei_O_Intel
Employee
139 Views

Hi there

 

Nope. If you are setting the LVDS to external PLL mode, you need to connect necessary pins from IOPLL to those pins, else Quartus will be flagging error. You can refer the connection from:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_altera_lvds-...

 

 

Thanks.

Eng Wei

silenfax
Beginner
119 Views
Reply