FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5984 Discussions

How can i use Quad SPI to talk with Flash memory ?

senjd
Novice
673 Views

I am trying to access Flash memory (MT25Q128) by using Quad SPI Ip (AS x4).

I am driving Quad SPI from PCIe. But i didn't understand the sequence to follow from IP document. Quad SPI does have two ports (avl_csr & avl_mem). Which one i need to drive? when?

 

Is it possible to store the bit file or data while running the fpga?

what should be the sequence to talk to flash memory?

0 Kudos
9 Replies
Ahmed_H_Intel1
Employee
337 Views

Hi Kishan,

Thanks for this nice question.

The following link show a very useful example for Generic serial flash interface, Please download it and start from there. It is a free example.

https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-f...

 

Regards,

 

senjd
Novice
337 Views

hi thanks for the reply. i ll go through this link. ​

Ahmed_H_Intel1
Employee
337 Views

Hi,

Please let me know if you need more support.

Regards.

senjd
Novice
337 Views

hi, thanks for your reply

i wanted to know the sequence to follow​ for writing the data to flash memory from pcie.as per the Qspi Ip doc its bit confusing for avl_csr & avl_mem port. if you can help me it will be a great help.

senjd
Novice
337 Views

Hi @AhmedH_Intel​ ,

 

Thanks for your reply. This projects are connecting PCIe with external memory. I am trying with PCIe bar4 connecting to Quad SPI interface (CSR + MEM ports). I tried to run following commands on qspi ip using pcie to write something on flash memory.

but i feel i am missing something

control reg [7] = 0x6

control reg [8] = 0x1

control reg [7] = 0x1001

control reg [A] = 0x7C

control reg [8] = 0x1

 

//WRITING DATA TO MEMORY PORT OF QUAD SPI IP.

MEM [0] = 0x1

MEM [1] = 0x2

 

On the output side i am getting csn high-low pulses for sometime. & outdata of qspi changes between 0xEh & 0xFh.

 

Any help appreciate most.

Is there any other registers i need to take care for writing the data?

 

Thanks

 

Ahmed_H_Intel1
Employee
337 Views

Hi,

It isn't clear how your system is working, I cannot review just by a piece of code, Can you explain more?

Regards,

senjd
Novice
337 Views

Hi @AhmedH_Intel​ ,

 

Thanks for the response.

 

Here is the system level information.

architecture (system) path :

Host driver will write configuration & data from PCIe (Bar4) which is connected to QSPI IP ( avl_csr & avl_mem ) ports.

 

Sequence i followed is provided from intel quad spi document (page num 26) : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf

 

proc page_program { } {

global mp operating_protocols_setting control_register write_instr

master_write_32 $mp $operating_protocols_setting 0x00000222 //qspi configuration register (avl_csr port) to select 4 byte enable

master_write_32 $mp $control_register 0x00000101 //qspi configuration register (avl_csr port) to enable output

master_write_32 $mp $write_instr 0x00007034 //qspi configuration register (avl_csr port) for write instruction command on flash memory

master_write_32 $mp 0x00001000 0x1234abcd //qspi memory access port (avl_mem port) writing single DWORD into FLASH MEMORY

}

 

Problem statement : I am able to get the address (0x00001000) and data (0x1234abcd). But unable to get the command. Command is required to come first before address & data.

Not able to get the proper sequence from intel. Can you help me out for it?

 

Thanks in advance

Ahmed_H_Intel1
Employee
337 Views

Hi,

Thanks for your sharing, can you please show a screenshot of the Qsys and the Top-level? this will help us.

Regards

Reply