Intel 40G Low latency IP RX PCS Ready status low

[MuralikumarM]

Hi,

I am using intel 40G low latency IP core with Base KR4 and Optical versions. in Both a cases i am facing issues in getting PCS READY status as HIGH.

Nothing is available in the design and only 40G IP core instance is created. one compilation the PCS ready is High and stable. in another compilation PCS ready LOW and further compilation PCS ready toggling.

Same hardware setup with different files are tried and these are results.

There is no timing violation observed in the design. 

Please let me know if you have any idea about this issue...

Thanks

MK

[ZiYing_Intel]

Hi MK,

Thanks for submitting the issue.

Please do let me have some time to investigate on your case and I will be get back to you with findings.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi MK,

I think it might be the Ethernet link issue.

In addition, your IP core can experience loss of signal on the Ethernet link after it is established. In this case, the TX functionality is unaffected, but the RX functionality is disrupted. The following symptoms indicate a loss of signal on the Ethernet link:

• The IP core deasserts the rx_pcs_ready signal, indicating the IP core has lost alignment marker lock.

• The IP core deasserts the RX PCS fully aligned status bit (bit [0]) of the RX_PCS_FULLY_ALIGNED_S register at offset 0x326. This change is linked to the

change in value of the rx_pcs_ready signal.

• If Enable link fault generation is turned on, the IP core sets local_fault_status to the value of 1.

• The IP core triggers the RX digital reset process.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi MK,

Since the case has been idle without further inquiries, I now close the case. If you have any inquiries after the close case, please do feel free to submit the another issue. There will have the specialist reach out to you to help you solve the problem.

Best regards,

Zi Ying

[MuralikumarM]

Hi,
May i know, why the link establishment is failing? And how to overcome this situation?

Regards
MK

[ZiYing_Intel]

Hi MK,

Can I get your .qar file? So that I can try debug the problem from my side.

Best regards,

Zi Ying

[MuralikumarM]

Sure I will send you by today morning 10 am IST.

[MuralikumarM]

Dear Zi Ying,

Please share your mail contact, so that I can share the .qar file link directly.

[MuralikumarM]

Hi ZiYing,

Design file was uploaded and link was sent to your mail. Please check and support.

Thanks

MK

[ZiYing_Intel]

Hi MK,

I compile your design file from my side already. The compilation is ok but I found that it got a lot warning inside there. Please do try initialize all the address because the Quartus will initialize the uninitialized addresses to 0. In shortly, it might be one of the reason that make the PCS ready signal toggling.

Best regards,

Zi Ying

[MuralikumarM]

Hi ZiYing,
May I know, which addresses need to be assigned, either in the ip core ports or in the top module registers.?

Regards
MK

[ZiYing_Intel]

Hi MK,

Please do try with the IP core registers first.

Best regards,

Zi Ying

[MuralikumarM]

Hi Zi Ying,

I have checked my design and found the registers are already mapped properly.

Are you talking about the reconfiguration registers and status registers are not assigned??

Regards

MK

[ZiYing_Intel]

Hi MK,

You may refer to the compilation report. I suggest you to have a look on the warning inside the compilation report and then solve problem according the warning message generated.

Best regards,

Zi Ying

[MuralikumarM]

Zi Ying,

Most of the warnings are generated and shown inside the ip core only. what could be the method to remove these warnings..???

Regards

MK

[ZiYing_Intel]

Hi MK,

Since the compilation is ok and there are a lot of factors that may cause the rx_pcs_ready not stable. You may check back to your clock frequency to make sure that you follow the clock frequency that suggested in the UG. Besides that, it might be the wrong connection of the IP core also. 

Please do check back your clock frequency and the port connection. Thanks.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi MK,

Since long time no hear feedback from you, I am now set this case into close case. If you have any question after the case closed, please do feel free to submit another issue.

Best regards,

Zi Ying