Intermittent PCIE LTSSM stuck at Detect Quiet

[Altera_Forum]

Hi 

 I had an intermittent issue during power-up or reset. Sometimes it works and the ltssm state is at L0. sometimes it is not working and the ltssm state is stuck at Detect.quiet.  Anyone encounter this problem? Any advice what is the problem?  Regards

[Altera_Forum]

Please see http://www.altera.com/literature/ug/ug_s5_pcie.pdf#page=316 

 If you are stuck in detect.quiet it sounds like you might not be exiting reset correctly. Check the signal voltage levels into the FPGA conform to PCIe 3.3V spec.

[Altera_Forum]

Hi all, in my case LTSSM signal is stuck at POLLING.COMPLINCE mode and not going to POLLING.CONFIG mode. 

 To check the problem i am using signal tap 2. when i am monitoring some signals like clocks: fixedclk, pld_clk, clb_clk, like all clocks are coming and pll_locked,rx_freq_locked are coming. resets : pcie_rstn, npor,rx_digitalreset,app_rstn all reset signals are coming and reset status signal is also zero. But and when i monitored test out signal nothing is coming. so, please suggest me what to do in my case, i am not finding where the exact problem is? is there any chances to go wrong in ip core or the problem is in my custom board?

[Altera_Forum]

How is test_in set, please ensure that Table 4-24 is followed: 

http://www.altera.com/literature/ug/ug_c5_pcie_avst.pdf#page=88 test_in[0] = 0; test_in[4:1] = 4'b0100; test_in[6:5] = 2'b00; test_in[31:7] = 25'h1;  If on hardware ensure that the correct AC caps are fitted to the links.

[Altera_Forum]

hi sir, 

i followed that table and checked the capacitor values.we are placing 0.1 uf on the tx lines and 0 ohm resistors on the rx lines. but still the same problem.please tell me how to get rid of it.  please send me any guide that have description about ltssm states and the what are the compulsory requirements for ltssm states has to go into the POLLING.CONFIG state.

[Altera_Forum]

1) make sure to hook up the transceiver reconfiguration controller to the PCIe core. 

2) make sure refclk is stable at 100MHz before the FPGA image configuration complete.