JESD204b -- How Many Device Clocks

[cdrennan]

I am specifying an FPGA module that implements an JESD204b interface with an Arria 10 device.  I have 4 each ADC devices that have 2 serial data lanes each (16 lanes total).   The transceiver blocks on the FPGA come 6 per block.  The puzzle is:

1.  How many transceiver blocks will I need to use ?

2.  Will I need to run an individual JESD204b Device Clock from the device-clock/sysref management circuit to every blocks clock reference pin or can one device clock be distributed  on the "xN" internal Arria 10 clock network ( or some other method)?

3.  Maximum Serializer/Deserializer frequency is expected to be below 6 Gbps.

[Kshitij_Intel]

Hi,

Can you please share the exact OPN or which dev kit you are using?

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi,

Please go through the AN 803: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Arria® 10 JESD204B RX IP Core 

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi,

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Thank you

Kshitij Goel