I am specifying an FPGA module that implements an JESD204b interface with an Arria 10 device. I have 4 each ADC devices that have 2 serial data lanes each (16 lanes total). The transceiver blocks on the FPGA come 6 per block. The puzzle is:
1. How many transceiver blocks will I need to use ?
2. Will I need to run an individual JESD204b Device Clock from the device-clock/sysref management circuit to every blocks clock reference pin or can one device clock be distributed on the "xN" internal Arria 10 clock network ( or some other method)?
3. Maximum Serializer/Deserializer frequency is expected to be below 6 Gbps.
