Low Latency 10 G Ethernet on Stratix 10 SX dev kit

[ZaidSahawneh]

Hello,

I am trying to run the 10G LL Ethernet example design on a Stratix 10 SX dev kit board.

The protocol is out of reset. Signal Tap reports the tx and rx paths to be ready. 

I am trying to confirm functionality using a loopback module and Intel's loopback testing scripts.

The attached file is the output I am getting from running 'gen_conf.tcl', 'monitor_conf.tcl', 'show_stats.tcl' in that order. I've gotten results once where more of the RX stats weren't '0' but I haven't been able to reproduce it. 

It doesn't seem to be functioning but I am not sure what I've missed. I think it may be due to the CSR primary input  pins? I'm not sure how to assign those pins so I am just using the fitter's automatic placements.

Primary input master_reset_n is assigned to PIN_A26 which is pushbutton 0.

TX serial data is assigned to PIN_BJ4 which is the tx of the SFP+ port

RX serial data is assigned to PIN_BH9 which is the rx of the SFP+ port

ref_clk_clk is tied to PIN_AT9 which is the reference clock of the SFP+ port

csr_clk is tied to PIN_AN27 which the dev kit documentation says is connected to the 148.5 MHz clock

      using intel clock controller, the ref clock (defaulted to 644.53125) was set to 322.265625 and the 148.5 clock was set to 125.

The reset controller input clock was set to 125 (was originally 148)

the pll ref clock frequency was set to 322.265625 (was originally 644.53125)

the atx pll ref clock frequency was set to 322.265625 (was originally 644.53125)

the phy rx_pma ref clock was set to 322.265625 (was originally 644.53125)

I know the example design is made for a GX board, not an SX, but my understanding is the only difference is the SX has an ARM HPS which I don't think would cause any issue. 

I'm new to working with these protocols. Any and all help is greatly appreciated. Thank you,

[ZaidSahawneh]

I realized I had the CSR signals were pulled up to the top level primary input/output from an early experiment when by default they are wired to 0s in the instantiation of altera_eth_10g_mac_base_r within altera_eth_top. I returned them to the default set up and the results changed minimally. The show_stats.tcl output reports the following attached.

How should I be addressing these signals? There is already a JTAG to AVMM module in the example design but I'm not sure how to access it via System Console (new to the tool) to perform my own reads and writes and the intel scripts are a bit confusing to ingest and repurpose.