MAX10 FPGA INTERNAL ADC

[sakthi_iitm]

I am working on the DC-DC power converter application. I utilize the internal ADCs of the MAX10 FPGA for sensing the current and voltages that required for the closed loop control of the power converter.

Can I please know the best way to invoke the Internal ADC in the software?

1. Using Nios II with Avalon MM interface for transmitting the data to the error generator block ( VHDL Soft IP core).

or

2. Accessing the ADC Vale by making a soft IP ADC core to send data to the error generator block ( VHDL Soft IP core). 

Also suggest me resources for the implementation of the same.

[sstrell]

I'm not sure what "ADC Vale" is.  Your option is #1 but you don't have to use Nios as the control mechanism.

Training:

https://learning.intel.com/developer/learn/course/external/view/elearning/337/introduction-to-analog-to-digital-conversion-in-intelr-maxr-10-devices

[sakthi_iitm]

It was a typing error.

It's 'ADC Value' !!!

[Farabi]

Hello, 

You can find how to build ADC design from this video: https://www.youtube.com/watch?v=0oO1RFa-4Xk

Unfortunately, Intel does not provide custom design example as per request.  

You can find the design example list here : https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-examples-overview.html?query=adc&currentPage=1

regards,

Farabi

[Farabi]

Hello,

This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,
Farabi